Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2008-09-02
2008-09-02
Peugh, Brian R. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C365S230050, C365S230080, C711S109000, C711S131000, C711S149000, C711S150000, C711S151000
Reexamination Certificate
active
11015959
ABSTRACT:
A synchronous multi-port memory including a plurality of ports coupled with a memory array, each of the plurality of ports including a delay stage to delay a memory access while a memory access arbitration is performed. The synchronous multi-port memory may also include selection logic coupled with the plurality of ports and the memory array to arbitrate among a plurality of contending memory access requests, to select a prevailing memory access request and to implement memory access controls.
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Blakely , Sokoloff, Taylor & Zafman LLP
Cypress Semiconductor Corporation
Parikh Kalpit
Peugh Brian R.
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