Electrical computers and digital processing systems: memory – Address formation – Combining two or more values to create address
Reexamination Certificate
2000-09-27
2004-03-30
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Combining two or more values to create address
C711S217000, C710S026000, C710S030000
Reexamination Certificate
active
06715058
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the data processing apparatus and, more particularly, to the specialized high performance processor units generally referred to as digital signal processing units. The invention relates specifically to addressing of the signal groups in the time-division multiplexed format.
2. Background of the Invention
Digital signal processing units have been developed as specialized data processing units. These units are optimized to perform routine, albeit complex, operations with great efficiency. For many applications, the computations need to be done in as close to real time as possible. In order to achieve the computational speed required of the digital signal, the digital signal processing units are optimized to perform the specified processing operation(s) with great efficiency. In addition, many of the functions that would be performed by a general purpose processing unit are eliminated or the functions performed outside of the core processing unit.
Referring to
FIG. 1
, a digital signal processing unit
1
having two digital signal processors, according to the prior art, is shown. A first digital signal processor
10
includes a core processing unit
12
(frequently referred to as a processing core), a direct memory access unit
14
, a memory unit or memory units
16
, and a serial port or serial ports
18
. The memory unit
16
stores the signal groups that are to be processed or that assist in the processing of the signal groups to be processed by the core processing unit
12
. The core processing unit
12
performs the bulk of the processing of signal groups in the memory unit. The direct memory access unit
14
is coupled to the core processing unit
12
and to memory unit
16
and mediates the signal group exchange therebetween. The serial port
18
exchanges signal groups with components external to the digital signal processing unit
1
. The core processing unit
12
is coupled to the serial port
18
and to the memory unit
16
and controls the exchange of signal groups between these components.
The digital signal processor is typically designed and implemented to have limited functionality, but functions that must be repeated and performed rapidly. The fast fourier transform calculation and the Viterbi algorithm decoding are two examples where digital signal processors have been utilized with great advantage. To insure that the digital signal processors operate with high efficiency, the core processing is generally optimized for the performance of the limited functionality. Part of the optimization process involves the off-loading, to the extent possible, any processing not directed toward the optimized function. The exchange of signal groups involving the core processing unit and the memory unit has been assigned to the direct memory access unit. The direct memory access unit also controls the exchange of as much as possible the optimization takes the form of off-loading to the extent possible.
More recently, the direct memory access controller has been implemented to control the exchange of data groups between the serial port and the memory unit. This implementation is described in the. U.S. Patent Application entitled APPARATUS AND METHOD FOR THE EXCHANGE OF SIGNAL GROUPS BETWEEN A PLURALITY COMPONENTS AND A DIRECT MEMORY ACCESS CONTROLLER IN A DIGITAL SIGNAL PROCESSSOR, cited above. Referring to
FIG. 2
, the digital signal processor
10
has a core processing unit
12
, a direct memory access controller
24
, a memory unit
16
, and a serial port
18
, the same components as in the prior art digital signal processors shown in FIG.
1
. The difference between the embodiments in FIG.
1
and
FIG. 2
is as follows. In
FIG. 1
, the direct memory access controller
14
, controls the exchange of signal groups between the memory unit
16
, and the core processing unit
12
. In
FIG. 2
, the direct memory access controller
24
controls not only the exchange of signal groups between the memory unit
16
, and the core processing unit
12
, but also controls the exchange of signal groups between the memory unit
16
and the serial port
18
. With this implementation, the core processing unit
12
is relieved of further processing responsibilities, as compared to the implementation shown in FIG.
1
. For example, the signal groups applied to the serial port can have a variety of addressing formats. Thus, the core processing unit
12
can be further optimized for specific processing operations without having to provide for these processing functions. The direct memory access controller
24
can be analogized to a plurality of controllable switches. The switches provide controllable channels for the transfer of signals between components. (In the preferred embodiment of the digital signal processors, typically two memory units and two serial ports are present. Consequently, a larger number of channels are provided. In the preferred embodiment, six channels are available in the direct memory access controller
24
.)
Transmission of signal groups between a digital signal processing unit and a external component frequently takes the form of a time-division multiplexed series of signal groups. Two examples of time-division multiplexed transmission of signal groups transmission are referred to as a T
1
protocol (U.S.) having 24 elements per frame and an E
1
protocol (Europe) having 32 elements per frame. Referring to
FIG. 3
, an illustration of the organization of the E
1
protocol is illustrated. As indicated in
FIG. 3
, the data is transmitted in blocks of signal groups (i.e., four elements per block is shown). The blocks of signal groups have the same number of signal groups as a frame of signal groups, but the organization is different. The first block includes, for example, the elements at the same location from each frame. The first block of elements include, in the U.S. protocol, element
0
from each frame. In other words, the first (
0
) block of transmitted signals groups is: frame
0
, element
0
; frame
1
, element
0
, through frame
23
, element
0
. The next block (
1
) of transmitted signal groups includes frame
0
, element
1
; frame
1
, element
1
; frame
2
, element
1
: through frame
23
, element
1
. The last block (
23
) of transmitted signal groups is: frame
0
, element
23
; frame
1
, element
23
; through frame
23
, element
23
.
The signal groups transmitted in this manner are not suitable for processing. These signal groups must be sorted into a frame of elements wherein each frame includes related elements in the numerical order and stored in the memory unit
16
. In this manner, the signal groups are readily available to the core processing unit
12
.
A need has therefore been felt for apparatus and an associated method having a feature that the addresses of the signal groups transmitted with a time-division multiplexed protocol can be modified and sorted into addresses suitable for processing by digital signal processing unit. This sorting address mode would have the further feature that the addresses of the signal groups would be modified and each signal group of a frame would be stored in order. It is a still further feature of the present invention that the sorting mode addressing procedure can be performed rapidly.
SUMMARY OF THE INVENTION
The aforementioned and other features are accomplished, according to the present invention, by providing address apparatus implemented with an efficient sorting mode of operation. In the sorting mode, the elements of a transmitted time-division multiplexed signal are addressed in the first frame order and, within each frame order. The addressing apparatus accomplishes this sorting by addressing the first element in the first block of transmitted elements, then addressing the first element in the second block of transmitted data, then addressing the first element in the third block, and so forth until the first element in each of the blocks has been addressed. In this manner, the elements of the first frame have
Nguyen Tai H.
Smith Patrick J.
Brady W. James
Holloway William W.
Nguyen Hiep T.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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