Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2003-03-13
2004-11-16
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S189110, C365S203000
Reexamination Certificate
active
06819612
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the field of microelectronic integrated circuits. Specifically, the present invention relates to a sense amplifier circuit that is capable of sampling and holding a reference voltage.
BACKGROUND ART
A flash or block erase memory (flash memory), such as, Electrically Erasable Programmable Read-Only Memory (Flash EEPROM), includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory as a whole are made smaller by eliminating the independent nature of each of the cells. As such, all of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide Semiconductor (MOS) memory cells that are field effect transistors (FETs). Each FET, or flash, memory cell includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block. The flash memory cell provides for non-volatile data storage.
A typical configuration of a flash memory cell consists of a thin, high-quality tunnel oxide layer sandwiched between a conducting polysilicon floating gate and a crystalline silicon semiconductor substrate. The tunnel oxide layer is typically composed of silicon oxide (Si
x
O
y
). The substrate includes a source region and a drain region that can be separated by an underlying channel region. A control gate is provided adjacent to the floating gate, and is separated by an interpoly dielectric. Typically, the interpoly dielectric can be composed of an oxide-nitride-oxide (ONO) structure.
The flash memory cell stores data by holding charge within the floating gate. In a write operation, charge can be placed on the floating gate through hot electron injection, or Fowler-Nordheim (F-N) tunneling. In addition, F-N tunneling can be typically used for erasing the flash memory cell through the removal of charge on the floating gate.
Prior Art
FIG. 1
is a circuit diagram of a portion of an array
100
of memory cells arranged in a NOR type of configuration. The array
100
contains non-volatile flash memory cells arranged in rows and columns. A plurality of word lines
110
, or select lines, are coupled to a plurality of rows of memory cells. The plurality of word lines
110
include WL
1
, WL
2
, WL
3
, and WL
4
. Each of the plurality of word lines
110
are coupled to gate regions of memory cells in their respective rows. For example, WL
1
is coupled to gate regions of memory cells defined by WL
1
-B
1
, WL
1
-BL
2
, WL
1
-BL
3
, and WL
1
-BL
4
, etc.
In addition, a plurality of bit lines
120
are coupled to a plurality columns of memory cells. The plurality of bit lines
120
include BL
1
, BL
2
, BL
3
, and BL
4
. The plurality of bit lines are coupled to drain regions of memory cells in their respective columns. For example, BL
1
is coupled to drain regions of memory cells defined by WL
1
-BL
1
, WL
2
-BL
1
, WL
3
-BL
1
, and WL
4
-BL
1
.
A plurality of source lines
130
are coupled to each of the rows of memory cells. The plurality of source lines include SL
1
, SL
2
, SL
3
, and SL
4
. In one example, each of the plurality of source lines
130
are coupled to source regions of memory cells in their respective rows. For example, SL
1
is coupled to source regions of memory cells defined by WL
1
-BL
1
, WL
1
-BL
2
, WL
1
-BL
3
, and WL
1
-BL
4
, etc. In another case, all the source lines are coupled together to form a common source line.
In the array
100
of memory cells, a particular memory cell can be identified and read to determine if the cell is programmed or erased by applying the correct voltages to a corresponding bit line and word line. For example, in order to read the memory cell
140
, appropriate voltages would be applied to bit line BL
2
and word line WL
2
to read the state of memory cell
140
. Correspondingly, in order to read the memory cell
150
, appropriate voltages would be applied to bit line BL
4
and word line WL
2
to read the state of memory cell
150
.
The plurality of bit lines
120
can be used to read current from identified memory cells in the array
100
of memory cells. For example, in order to determine the state of memory cell
140
, appropriate voltages are applied to BL
2
, SL
2
, and WL
2
. When selected and activated, the memory cell
140
will produce a current through its respective drain region that is read from the bit line BL
2
.
In reading the memory cell
140
, the current from bit line BL
2
passes through the transistor
194
that is activated by the select circuit
190
. The select circuit
190
selects either transistor
192
and
194
to read current from bit line BL
1
and BL
2
, respectively. After passing through the transistor
194
and the select circuit
190
, the current on BL
2
goes to the sensing circuit
160
. The sensing circuit
160
compares the voltage corresponding to the current from BL
2
with the reference voltage supplied along line
170
to determine whether the memory cell is in a programmed (0) or erased (1) state.
For example, if the current from memory cell
140
is less than the reference current, then the memory cell
140
is in a programmed state (0), and its corresponding threshold voltage (VT) is very high and should be higher than the reference voltage generated by the voltage generator
180
of the reference cell. Correspondingly, if the current from memory cell
140
is more than the reference current, then the memory cell
140
is in an erased state (1), and its corresponding VT should be lower than the reference voltage.
Correspondingly, select circuit
195
selects either transistor
196
and
198
to read current from bit line BL
3
and BL
4
, respectively. The voltage corresponding to the current from the bit lines BL
3
and BL
4
is compared to the reference voltage from the reference voltage generator
180
in the sensing circuit
162
.
The reference voltage and a corresponding reference current (i.e., reference signals) are generated from a circuit
180
independent of the array
100
of memory cells. The reference voltage and reference current are then delivered throughout the array
100
of memory cells for use in reading the state of individual memory cells. The distribution of the reference voltage and current throughout the array
100
of memory cells becomes more difficult and expensive as voltage outputs of power supplies used to operate devices containing the array
100
of memory cells are reduced in magnitude.
Specifically, a variation in reference voltages and reference currents will exist due to line resistance used for distributing the reference signals throughout the array
100
of memory cells. Simply put, there is a degradation in the reference signal the further from the location where the reference signals are generated. For example, line resistance R
ref
exists between each of the sensing circuits (e.g., circuit
160
and
162
). As a result, the reference voltage taken along line
170
will vary depending on how much line resistance R
ref
is encountered.
To compensate for this variation in the reference voltage due to line resistance, a margin for error is tolerated between the reference signals and the sensed signals to properly determine a programmed or erased state. However, as operating voltages are reduced, the margin for error also becomes smaller. As such, fabrication tolerances also must meet tighter tolerances to compensate for the reduced margin for error, and could result in lower yields.
Furthermore, high power amplifiers in the periphery of a memory device are used to magnify the difference in signal strength between the reference signal and a signal coming from a memory cell in the array
100
of memory cells. These high power amplifiers take up critical space in memory device especially as the size of the memory device is reduced.
Moreover, the high power amplifiers continually consume power when the device containing the array
100
of memory cells is operating. Whether or not the any of the memory cells in the array
100
is b
Advanced Micro Devices , Inc.
Elms Richard
Nguyen Hien
Wagner , Murabito & Hao LLP
LandOfFree
Apparatus and method for a sense amplifier circuit that... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for a sense amplifier circuit that..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for a sense amplifier circuit that... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3347042