Electronic digital logic circuitry – Multifunctional or programmable – Sequential or with flip-flop
Reexamination Certificate
2003-06-05
2004-11-30
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Sequential or with flip-flop
C326S095000, C327S144000, C365S156000, C365S189050
Reexamination Certificate
active
06825691
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to latch circuitry and more particularly to radiation resistant latch circuitry with integrated scanning capability.
2. Related Art
Various latching circuits are known for isolating logic circuitry stages, such as for ensuring orderly evaluation without corrupting data from one logic stage to the next, for avoiding races, and for other timing purposes. In complicated logic circuitry, such as that of a microprocessor or an application specific integrated circuit, it is known to “scan” data in and out of the logic circuitry latches in order to verify proper operation of the circuitry. It is also known to integrate scanning capability into latches. For example, U.S. Pat. No. 5,896,046, “Latch structure for ripple domino logic,” Apr. 20, 1999, Bjorksten et al.,
FIG. 2
discloses a domino latch with integrated scanning, and is hereby incorporated herein by reference.
Referring now to
FIG. 1
herein, a latch
101
with integrated scanning is illustrated. Latch
101
is a simplified version of that disclosed by Bjorksten et al. The latch
101
includes conventional latch circuitry
100
, a first scanning-mode control switch
160
, consisting of a PFET/NFET pair of passgates, coupled to the output node of the latch circuitry
100
, and a second scanning-mode control switch
170
interposed between the output node of the latch circuitry
100
and a scanning-mode latch
150
.
One problem with prior art latches is that cosmic rays and alpha particles can collide with a latch node and cause it and an output to switch states erroneously. The related patent application, cross-referenced above, discloses improvements in radiation immunity for latches, however, it does not address latches with integrated scanning such as latch
101
of
FIG. 1
suggested by Bjorksten et al. Therefore a need exists for improvements in radiation immunity for latches with integrated scanning.
SUMMARY OF THE INVENTION
The foregoing need is addressed in the present invention. In one form of the invention, a radiation resistant latch has an overall output node, and first, second and third sublatches. The sublatches each have input circuitry, an output node coupled to the sublatch's input circuitry and feedback circuitry coupled to the sublatch's output node for reinforcing an output signal of the sublatch. The sublatches are operable to receive a data signal at their respective input circuitry and responsively generate binary-state output signals on their respective output nodes. The output node of at least the first sublatch is coupled to the latch output node. The output nodes of the second and third sublatches are respectively connected in the latch such that if any one of the three sublatches is subjected to a radiation induced erroneous change of state, the output signals of the other two sublatches reduce an effect of the change on an overall output signal for the latch, providing improved radiation immunity. The latch also includes a number of scanning-mode control switches coupled to ones of the sublatches for scanning data into the latch.
Additional objects, advantages, aspects and other forms of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings.
REFERENCES:
patent: 5504703 (1996-04-01), Bansal
patent: 5896046 (1999-04-01), Bjorksten et al.
patent: 6629276 (2003-09-01), Hoffman et al.
“Twice Redundant Radiation Hardened Latch,” IBM Technical Disclosure Bulletin, vol. 30, No. 8, Jan. 1988, pp. 248-249.
D.B. Eardley, “Latch Circuit Insensitive to Disturb by Alpha Particles,” IBM Technical Dislcosure Bulletin, vol. 24, No. 12, May 1982, pp. 6461-6462.
“On-Chip Logic Enhancements for Test of Error Checking and Correcting Related Functions in On-Card Applications,” IBM Technical Disclosure Bulletin, vol. 30, No. 12, May 1988, pp. 247-250.
Chu Sam Gat-Shang
Klim Peter Juergen
Lee Michael Ju Hyeok
Paredes Jose Angel
Chang Daniel D.
England Anthony V. S.
McBurney Mark E.
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