Apparatus and method for a programmable logic device having...

Electronic digital logic circuitry – Multifunctional or programmable – Array

Reexamination Certificate

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C326S046000

Reexamination Certificate

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07598769

ABSTRACT:
A programmable logic device including a plurality of logic elements organized in an array. Each of the logic elements includes an N-stage Look Up Table structure having 2Nconfiguration bit inputs and a Look Up Table output. The first stage of the Look Up Table includes 2Ntri-state buffers coupled to receive the 2Nconfiguration bit inputs respectively. A decoder, configured from logic gates, is coupled to receive to one or more Look Up Table select signals and to generate a set of control signals to control the 2Ntri-state buffers so that one or more of the 2Nconfiguration bit inputs is selected by the first stage. The configuration bits are then provided to subsequent muxing stages in the Look Up Table.

REFERENCES:
patent: 5399925 (1995-03-01), Nguyen
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“STRATIX II Device Handbook, vol. 1 and vol. 2” Altera Corporation, May 2007, Downloaded from: http://www.altera.com/literature/hb/stx2/stratix2—handbook.pdf, on Oct. 3, 2007, vol. 1 : pp. 1-1 to 6-2 vol. 2 : pp. 1-1 to 11-32.
“STRATIX II Architecture,” Altera Corporation, May 2007, downloaded form: http://www.altera.com/literature/hb/stx2/stx2—sii51002.pdf, on Oct. 3, 2007, pp. 2-1 to 2-106.
“VIRTEX 4 Family Overview,” Xilinx, Inc., DS112 (v1.3) Mar. 26, 2005, Downloaded from: http://picocomputing.com/pdf/www/E-12/Third%20Party%20Manuals/Virtex-4%20FPGA/Virtex-4%20Overview%20V1.3.pdf, on Oct. 3, 2007, pp. 1-9.
“STRATIX Architecture,” Altera Corporation, Jul. 2005, downloaded from http://www.altera.com/literature/hb/stx/ch—2—vol—1.pdf on Oct. 6, 2007, pp. 2-1 to 2-140.

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