Boots – shoes – and leggings
Patent
1997-01-06
1999-03-30
Sheikh, Ayaz R.
Boots, shoes, and leggings
36476003, 36476005, G06F 752
Patent
active
058896910
ABSTRACT:
In a multiplier unit having a preprocessor stage, a multiplier stage, and a summation stage, the multiplier stage includes a shift register, a gate component for controllably transmitting the multiplicand A in a manner determined by a bit signal of multiplier B applied to the gate component control terminal. Partial products are grouped by multiplicand digits and each digit is applied, through delay components determined by the order of the digit, to first terminals of an associated adder components. Output signals from each adder component is transmitted through a plurality of delay components and applied to second input terminals of the same adder component. In this manner, partial products A.sub.p *B.sub.q are assembled and the partial products (A.sub.0 + . . . A.sub.M)*B.sub.q =A*B.sub.q can be applied to the summation unit in a single period. When the multiplier is an integer multiple of the multiplicand, the implementation is particularly convenient.
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Gatherer Alan
Lemonds Carl E.
Brady W. James
Donaldson Richard L.
Hoel Carlton H.
Lee Douglas S.
Sheikh Ayaz R.
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