Apparatus and method for a memory unit with a processor integrat

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

395442, 395474, 395479, 39520005, G06F 1316, G06F 1200

Patent

active

056780214

ABSTRACT:
A smart memory (10) is provided that includes data storage (12 and 18) and a processing core (14 and 16) for executing instructions stored in the data storage area (12 and 18). Externally, smart memory (10) is directly accessible as a standard memory device. In a first mode of operation, the smart memory (10) is a data storage facility for an associated central processing unit (22). In a second mode of operation, the smart memory (10) is a storage facility for the processing core (14 and 16) and for central processing unit (22) for simultaneous execution of instructions. The central processing unit (22) controls the mode of operation and determines the instructions executed by the processing core (14 and 16). The wide data bus, available with an integrated processor/storage facility, permits certain processing operations to be off-loaded to the smart memory (10) where the processing operations can be performed more efficiently.

REFERENCES:
patent: 3962682 (1976-06-01), Bennett
patent: 4314353 (1982-02-01), Gunter et al.
patent: 4349870 (1982-09-01), Shaw et al.
patent: 4368514 (1983-01-01), Persaud et al.
patent: 4823257 (1989-04-01), Tonomura
patent: 5088023 (1992-02-01), Nakamura et al.
patent: 5134711 (1992-07-01), Asthana et al.
patent: 5438666 (1995-08-01), Craft et al.
Tom Goodman, "Application-Specific RAM Architectures Attack New Applications," Wescon Conference Proceedings, 1986, pp. 1-5.
Steve Z. Szirom, "Intelligent Memories Promise Product and Market Niches," Wescon Conference Proceedings, 1989, pp. 24-28.
A. Asthana, et al., "An Intelligent Memory System," Computer Architecture News, 19.sub.--, pp. 12-20.
I. Aleksander, "Intelligent Memories and the Silicon Chip," IEE Electronics & Power, 1980, pp. 324-326.
Stephen Walters, "Memories with Internal Logic Cut External Circuit Needs," EDN, 1981, pp. 239-244.
Roderic Beresford, "Smart Memories Seek Honors in Proliferating Small Systems," Electronics, 1982, pp. 89-98.
Gary Wood, "Intelligent Memory Systems Can Operate Nonstop," Electronic Design, 1982, pp. 243-250.
P. Corsini, et al., "Intelligent Memory Subsystem Supporting Memory Virtualisation," Electronics Letters, 1983, pp. 265-266.
Karl Goser, et al., "Intelligent Memories in VLSI," Information Sciences 34, 1984, pp. 61-82.
Cecil Kaplinsky, et al., "Memory Controller Gives a Microprocessor a Big Mini's Throughput," Electronic Design, 1984, pp. 153-164.
M. Andrews, et al., "Concurrency and Parallelism -Future of Computing," Super Computing ACM, 1985, pp. 224-230.
Hartmut Schrenk, "Novel Chip Card Concept with the SLE 4401 K Intelligent Memory," Telecom Report 9, (1986) No. 3, 1986, pp. 172-176.
Robert Grondalski, et al., "Session XVI: Microprocessors-Special Purpose THPM 16.3: A VLSI Chip Set for a Massively Parallel Architecture", IEEE International Solid-State Circuits Conference, Feb., 1987, pp. 198, 199, 399, 400.
S. J. Bailey, "Intelligent Memories Strengthen Bonds between Central/Distributed Control," Control Engineering, Jun., 1987, pp 69-73.
Ron Wilson, et al., "Intelligent Memory Architectures Attack Real-World Computation," Computer Design, 1988, pp. 28-30.
A. F. Johnson, "Busting Imaging Barriers with a Mac II," ESD: THE Electronic System Design Magazine, Jul. 1988, pp. 79-82.
Masood Namjoo, et al., "Implementing SPARC: A High-Performance 32-Bit RISC Microprocessor," Sun Technology, Winter, 1988, pp. 42-48.
Abhaya Asthana, et al., "Impact of Advanced VLSI Packaging on the Design of a Large Parallel Computer," 1989 International Conference on Parallel Processing, 1989, pp. I-323 -I-327.
Patrice Bertin, et al., "Introduction to Programmable Active Memories," Digital Paris Research Laboratory, Jun. 1989, pp. 1-9.
Dik Lun Lee, et al., "HYTREM--A Hybrid Text Retrieval Machine for Large Databases," IEEE Transactions on Computers, Jan. 1990, pp. 111-123.
Don Speck, "The Mosiac Fast 512K Scalable CMOS dRAM," Advanced Research in VLSI 1991; UC Santa Cruz, 1991, pp. 229-244.
Alex Medelsohn, "Will Monolithic or Multichip Processors Win the Performance Race?," Computer Design, May, 1991, pp. 100-110.
Randy Groves, "Design Decisions and Technology That Were Keys to Success of RISC System/6000," Computer Design, May, 1991, pp. 112-114.
Gideon Intrater, "How High-Ended Embedded Processors Are Changing," Computer Design, May, 1991, pp. 116-121.
C. Y. Lee, "Intercommunicating Cells, Basis for a Distributed Logic Computer", Proceedings--Fall Joint Computer Conference, 1962, pp. 130-136.
C. Y. Lee, "A Content Addressable Distributed Logic Memory with Applications to Information Retrieval," Proceedings of the IEEE, 1963, pp. 924-932.
Chat-Yu Lam, et al., "The Intelligent Memory System Architecture -Research Directions," Department of Defense, Defense Technical Information Center, 1979, pp. 1-36.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Apparatus and method for a memory unit with a processor integrat does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus and method for a memory unit with a processor integrat, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for a memory unit with a processor integrat will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1561003

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.