Apparatus and method for a memory array with shallow trench...

Details Apparatus and method for a memory array with shallow trench... Apparatus and method for a memory array with shallow trench...

2004-07-20

2008-09-09

Nguyen, Dao H (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S316000, C257SE21681, C257SE21682, C365S185110, C438S257000, C438S776000

Reexamination Certificate

active

07423312

ABSTRACT:
The present invention provides an apparatus and method for a non-volatile memory comprising at least one array of memory cells with shallow trench isolation (STI) regions between bit lines for increased process margins. Specifically, in one embodiment, each of the memory cells in the array of memory cells includes a source, a control gate, and a drain, and is capable of storing at least one bit. The array of memory cells further includes word lines that are coupled to control gates of memory cells. The word lines are arranged in rows in the array. In addition, the array comprises bit lines coupled to source and drains of memory cells. The bit lines are arranged in columns in the array. Also, the array comprises at least one row of bit line contacts for providing electrical conductivity to the bit lines. Further, the array comprises shallow trench isolation (STI) regions separating each of the bit lines along the row of bit line contacts.

REFERENCES:
patent: 6512263 (2003-01-01), Yuan et al.
patent: 6570213 (2003-05-01), Wu
patent: 6570214 (2003-05-01), Wu
patent: 6674120 (2004-01-01), Fujiwara
patent: 6888753 (2005-05-01), Kakoschke et al.

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