Electrical computers and digital processing systems: support – Computer power control
Reexamination Certificate
2000-12-20
2004-08-31
Lee, Thomas (Department: 2115)
Electrical computers and digital processing systems: support
Computer power control
C326S083000
Reexamination Certificate
active
06785828
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to power consumption during I/O buffer clamping. In particular, the present invention relates to an apparatus and method for a low power multi-level GTL I/O buffer with fast restoration of static bias.
BACKGROUND OF THE INVENTION
The reduction of current and power consumption have become increasingly important in modern PC (personal computer) system designs, including, for example, the design of mobile computers, laptop computers, etc. Reduction of power consumption provides the direct benefit of increasing battery lifetime, which is vital for mobile or laptop computers. Unfortunately, due to the size of the various I/O (input/output) buffers utilized in modern PC systems, the interfacing signals between the various I/O buffers are subject to overshoot or undershoot when transitioning from zero to one or one to zero, respectively. In order to solve this problem, state of the art chipset I/O buffer circuits are designed with a P-clamp transistor and an N-clamp transistor to reduce overshoot and undershoot when interfaced with a CPU (central processing unit) I/O buffer circuit. The P-clamp transistor is used for preventing pad voltage overshoot, and the N-clamp transistor is used for preventing pad voltage undershoot.
These I/O buffer circuits normally include static and dynamic components. During a rising transition period from zero to one, the dynamic components pull down a P-bias node voltage from a static level (static mode) to a dynamic level (dynamic mode) and turn-on the P-clamp transistor. Once turned on, the P-clamp circuit conducts to generate a clamping current from a GTL (gunning transistor logic) buffer, external termination voltage (Vtt) supply to the I/O buffer ground (IOVSS) through an I/O buffer pad. The clamping current generated by the P-clamp is in the magnitude of milli-amperes (mA) range and is used to provide overshoot protection. For example, referring to
FIG. 1
, a rising transition from a zero to a one is depicted at the I/O buffer pad. When a voltage overshoot
104
at the pad is detected, the pad is clamped down to the Vtt level
106
for an overshoot event greater than the Vtt voltage level
106
. However, once the transition is over, the P-bias node voltage must return to the static voltage level immediately and turn-off P-clamp circuit.
The static voltage level is normally designed with a P-clamp voltage between state and source (VGS) at about 50 milli-volts (mV), which is much less than a threshold voltage (Vtp) (0.4-0.5 volts) of the P-clamp transistor. As a result, the P-clamp transistor is in a cutoff region and only nano amperes of the leakage current flow through the P-clamp transistor during static mode. However, if the return or restoration of the P-clamp transistor, from dynamic mode to static mode, is not fast enough, then a considerable amount of extra current in the range of milliamperes will be unnecessarily consumed. This results in large power consumption and consequently drains the system battery quickly.
Referring again to
FIG. 1
, the time in which clamping of the pad voltage level to the Vtt voltage level
106
is indicated as &tgr;
on
112. &tgr;
on
refers to the duration of time during which the P-clamp transistor is activated
108
until the time the P-clamp transistor is deactivated
110
. Unfortunately, during this &tgr;
on
112 period, the P-clamp circuit is using up power by generating a clamping current as described above. Ideally, after the rising transition period &tgr;
on
112 is over, the P-bias node voltage level returns to the static voltage level as quickly as possible to ensure that the P-clamp circuit consumes the least amount of current from Vtt external voltage supply. Although the amount of voltage from Vtt external voltage supply during this &tgr;
on
period appears to be negligible, modern PC systems may include hundreds of I/O buffers, each requiring clamping of the pad voltage levels. As the amount of I/O buffers increases, the amount of current, and hence the amount of battery loss, is greatly increased.
Therefore, there remains a need to overcome one or more of the limitations in the above-described existing art.
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Blakely , Sokoloff, Taylor & Zafman LLP
Cao Chun
Intel Corporation
Lee Thomas
LandOfFree
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