Apparatus and method for a low power latchable adder

Details Apparatus and method for a low power latchable adder Apparatus and method for a low power latchable adder

1997-10-31

1999-11-23

Nelms, David

Electronic digital logic circuitry

Exclusive function

Half-adder or quarter-adder

326 49, 364712, 36418402, G05B 100

Patent

active

059907037

ABSTRACT:
A high speed, low power 3-2 adder (300, 500) with latchable outputs comprises a most significant bit (MSB) adder circuit (100) and a least significant bit (LSB) adder circuit (200). MSB adder circuit (100) includes three differential data inputs (A1, B1, and C1), a latch enable input (LE1), three separate bias points, and an MSB output. In addition the LSB adder circuit includes three differential data inputs (A2, B2, and C2), a latch enable input (LE2), three separate bias points and a LSB output. Internal latch circuits (172, 272) and latch enable circuits (174, 274) are provided in each adder stage. Internal latch enable inputs are connected in parallel in one configuration. Separate latch enable inputs are provide in a second configuration. Separate bias points are also provided in each adder stage.

REFERENCES:
patent: 4390962 (1983-06-01), Current
patent: 4916653 (1990-04-01), Shimizu et al.

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