Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2001-03-26
2004-04-06
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
Reexamination Certificate
active
06718453
ABSTRACT:
BACKGROUND
1. Field
This invention relates to memory address translation, and more specifically to non-contiguous address translation tables in memory.
2. Background
A switched fabric network system may use a scheme of a translation protection table (TPT) for all memory registration. This table may be created in system memory, and allows a device to read the table to gain access to a physical address, converted from a virtual address, for storage locations.
FIG. 1
shows a block diagram of elements existing at a processor node in a switched fabric system. An operating system
10
may communicate with a channel adaptor
12
to get a physical address translation. A channel adaptor
12
(e.g. host channel adaptor (HCA), target channel adaptor (TCA), etc.) may use a system memory
14
resident translation protection table in order to convert virtual addresses used by applications into physical addresses used by the channel adaptor
12
. In current channel adaptor designs, this table is required to be entirely contiguous in physical memory. Therefore, the operating system is required to lock a large piece of physical memory and keep it locked during all operations carried out by the channel adaptor.
FIG. 2
shows a diagram of connections between a channel adaptor and a contiguous TPT table. The dotted line separates the channel adaptor logic
12
from system memory
14
. System memory
14
contains a translation protection table
16
. Channel adaptor
12
includes a register
18
containing the table size, a register
20
containing the base physical address of the table, a comparator
22
, and an adder
24
. The channel adaptor hardware tracks the table size of TPT table
16
as well as the base physical address. The index is a portion of a virtual address from the operating system. Comparator
22
compares the received index with the table size stored in register
18
to determine if the index is out of the bounds of TPT table
16
, and if so, generates an “index out of bounds” error. If the index is not out of bounds, the address stored in register
20
is added to the index by adder
24
generating a physical address to TPT table
16
. A channel adapter stores information not only associated with the base of the to TPT table
16
, but also the number of entries in the table. For any given index into the TPT table, the channel adaptor is able to locate the physical address of the appropriate entry in the table as well as check the entry as outside the bounds of the TPT table.
TPT table
16
is a fixed size. However, the operating system may need, during the course of operation, to change the initial set up for the TPT table (e.g., in order to map additional memory pages for a recently started application). A problem exists if the operating system desires to grow the one and only TPT table in the system when it is currently being used by the channel adaptor. The operating system has two options to possibly solve this problem. First, the operating system may flush the current TPT table and move the entire table to a larger contiguous location in system memory (to allow for more entries to be mapped). This larger location may be very large, e.g., supporting mapping for 2
27
−1 physical pages of memory. A TPT table supporting even a fraction of this memory map can easily be gigabytes in size.
Second, the operating system may stop operations on the channel adaptor long enough to free up or rearrange the current TPT table to make room for the newly requested page mappings. Neither of these two options is desirable. The first option is unlikely to be able to locate a large portion of contiguous system memory that can fit the bigger TPT table. The second would require operations on the channel adaptor to be halted for a period of time while the TPT table is reorganized.
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Milenkovic, M. Microprocessor Memory Management Units. IEEE Micro, Apr. 1990.*
Tommy. Re: db_block_size and performance. [Online] news://comp.database.oracle.server, Oct. 1998.*
Teller et al. TLB consistency on highly parallel shared-memory multiprocessors. Proceedings of the 21st Hawaii International Conference on System Sciences, pp. 184-193, Jan. 1988.
Collins Brian M.
Reohr Dick
Choi Woo M.
Intel Corporation
Kim Matthew
Schwegman Lundberg Woessner & Kluth P.A.
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