Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-02-26
2002-11-05
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S754000, C257S755000, C257S756000, C257S905000, C257S906000, C257S907000, C257S908000
Reexamination Certificate
active
06476489
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor device adopting an interlayer contact structure for improving the electrical characteristics of the device by reducing the contact resistance between upper and lower conductive layers thereof, and a method of manufacturing the same.
As the integration of semiconductor devices increases, the formation of conductive layers having a multi-layered structure becomes more prevalent. In doing so, the contact characteristic (i.e., resistance) between such conductive layers has an important effect on the overall electrical characteristics of the semiconductor device. Recently, a conductive layer having a polycide structure (silicide atop polysilicon) has been employed to reduce sheet resistance.
FIGS. 1A-1D
illustrate a conventional method for making an interlayer contact between upper and lower conductive layers, each having the above-mentioned polycide structure, of a semiconductor memory device.
Referring to
FIG. 1A
, an oxide such as silicon oxide (SiO
2
) is deposited on a semiconductor substrate
10
to form a gate oxide layer
12
. Then, a first polysilicon layer
14
doped with phosphorus ions, a first tungsten silicide (WSi
x
) layer
16
and a capping layer
18
are sequentially deposited on the gate oxide layer
12
, and are then patterned to form a lower conductive layer out of the first polysilicon layer
14
and the first tungsten silicide layer
16
. The capping layer
18
is generally formed out of an oxide or nitride material. Then, an insulating material such as boro-phosphorus silicate glass is deposited over the first tungsten silicon layer
16
, and is reflowed to form an interlayer insulating layer
20
having a planer surface (see FIG.
1
B). A contact hole
1
is then formed by partially etching the interlayer insulating layer
20
and the capping layer
18
to expose the first tungsten silicide layer
16
(see FIG.
1
C). Subsequently, a second polysilicon layer
22
doped with phosphorus ions and a second tungsten silicide layer
24
are stacked over the interlayer insulating layer
20
and the second tungsten silicon layer to form an upper conductive layer. The contact layer is formed such that the second polysilicon layer
22
is in contact with first tungsten silicide layer
16
(see FIG.
1
D).
In this conventional interlayer contact structure, however, where the first tungsten silicide layer
16
directly contacts the second polysilicon layer
22
, and the second polysilicon layer
22
is doped with phosphorus ions, the contact resistance increases for two reasons. First, the phosphorus ions doped in the second polysilicon layer
22
diffuse toward the first tungsten silicide layer
16
, and serve to decrease the impurity concentration at the interface between the second polysilicon layer
22
and the first tungsten silicon layer. Secondly, after forming the contact hole
1
and prior to depositing the second polysilicon layer
22
, a natural oxide layer such as tungsten oxide (WO
3
) or silicon oxide (SiO
2
) forms on the surface of first tungsten silicide layer
16
.
FIG. 2
shows the contact resistance distribution characteristics measured in seven sample wafers (a) through (g) that adopt the conventional interlayer contact structure (FIG.
1
D). Here, it can be seen that the contact resistance of the conventional contact structure runs well above 1 k&OHgr; per contact (where the contact size is about 0.4-0.48 mm
2
) Such a high contact resistance negatively affects the operation speed and can even prevent proper device operation if it goes beyond about 10 kW.
FIG. 3
shows the impurities distribution in the contact structure described above, both before (a) and after (b) annealing. Concentrations are shown for the first polysilicon layer
14
, the first tungsten silicide layer
16
, the second polysilicon layer
22
, the second tungsten silicide layer
24
, and at every interface of these layers. Here, a low concentration of impurities is evident between the first tungsten silicide layer
16
and the second polysilicon layer
22
.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a semiconductor device having an interlayer contact structure for improving contact characteristics between upper and lower conductive layers of the semiconductor device, by lowering the contact resistance thereof.
It is another object of the present invention to provide a method of manufacturing the semiconductor device with the interlayer contact structure.
To achieve the above first, there is provided an interlayer contact structure in a semiconductor device, comprising: a first conductive layer; a first silicide layer formed over the first conductive layer; a second conductive layer doped with impurities; and a second silicide layer formed over second conductive layer, wherein the first and second conductive layers directly contact each other.
To achieve the above second object, there is provided a method of manufacturing an interlayer contact structure in a semiconductor device, the method comprising the steps of: forming a first conductive layer; forming a first silicide layer over the first conductive layer; forming an interlayer insulating layer over the first silicide layer; forming a contact hole by partially etching the interlayer insulating layer; partially etching the first silicide layer where the first silicide layer is exposed through the contact hole; forming a second conductive layer doped with impurities over the first conductive layer, the first silicide layer, and the interlayer insulating layer; and forming a second silicide layer over the second conductive layer.
It is preferable that the first and second conductive layers be made of amorphous silicon or polysilicon. It is further preferable that the first and second silicide layers be made of a material selected from the silicide group of tungsten silicide (WSi
2
), titanium silicide (TiSi
2
), molybdenum silicide (MoSi
2
), and tantalum silicide (TaSi
2
), and that the employed impurities be phosphorus or arsenic ions.
In the above method, it is preferable that the step of partially etching the first silicide layer be performed using an isotropic etching method. It is further preferable that the isotropic etching method be a wet etching method using an etchant containing NH
4
OH, H
2
O
2
and H
2
O, or a dry etching method using Cl
2
/SF
6
gas. During the step of partially etching the first silicide layer, the first silicide layer is etched until the first conductive layer is exposed.
Therefore, according to the semiconductor device adopting the interlayer contact structure and method of manufacturing the same, the electrical properties of the interlayer contact can be improved by lowering the contact resistance between the lower conductive layer having a silicide layer in its uppermost portion and the upper conductive layer having an impurities-doped conductive layer in its lowermost portion.
REFERENCES:
patent: 3777364 (1973-12-01), Schinella et al.
patent: 4329706 (1982-05-01), Crowder et al.
patent: 4398335 (1983-08-01), Lehrer
patent: 4507852 (1985-04-01), Karulkar
patent: 4556897 (1985-12-01), Yorikane et al.
patent: 4663825 (1987-05-01), Maeda
patent: 4751198 (1988-06-01), Anderson
patent: 4754318 (1988-06-01), Momose et al.
patent: 4887143 (1989-12-01), Okamoto et al.
patent: 4888306 (1989-12-01), Komatsu et al.
patent: 4943539 (1990-07-01), Wilson et al.
patent: 4948459 (1990-08-01), van Laarhoven et al.
patent: 5480837 (1996-01-01), Liaw et al.
patent: 5519254 (1996-05-01), Tabara
patent: 5619071 (1997-04-01), Myers et al.
patent: 5736770 (1998-04-01), Asai et al.
patent: 5801427 (1998-09-01), Shiratake et al.
patent: 6020641 (2000-02-01), Lee et al.
patent: 42 34 666 (1993-04-01), None
patent: 401039064 (1989-02-01), None
patent: 404072763 (1989-02-01), None
Ko Dae-hong
Lee Nae-in
Park Young-wook
Yoo Bong-young
Lee Eddie
Ortiz Edgardo
Samsung Electronics Co,. Ltd.
Volentine, L.L.C. Jones
LandOfFree
Apparatus and manufacturing method for semiconductor device... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and manufacturing method for semiconductor device..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and manufacturing method for semiconductor device... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2976702