Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2000-06-26
2003-04-15
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S055000, C326S113000, C327S065000, C327S215000
Reexamination Certificate
active
06549037
ABSTRACT:
BACKGROUND
To improve the performance capability of a microprocessor, it is often desirable to increase the speed or clock rate at which the microprocessor operates. Higher clock rates may be possible by reducing the amount of time it takes for a particular circuit within the microprocessor to process its input signals and provide its output signal. To this end, various dynamic logic circuits have been developed that have improved performance characteristics as compared to some traditional complementary metal-oxide semiconductor (CMOS) circuits. Examples of such dynamic logic circuits include domino logic circuits, skew tolerant domino circuits, latched domino circuits, differential domino circuits, and the like.
However, as the operational speed of the circuits within an integrated circuit is increased, race conditions within the integrated circuit may occur. To address the problems associated with race conditions, a clock is often used to synchronize the operation of circuits within the integrated circuit relative to each other. Examples of such circuits are summarized in Chapter Four of “Low-Voltage CMOS VLSI Circuit,” by Luo et al. (1999) and Chapter 5.7 of “Circuit Design for CMOS VLSI,” by John P. Uyemyra (1992).
The use of a clock may reduce the risk that the output provided by a fast circuit to a slower circuit changes before the slower circuit is able to properly process the output of the faster circuit. However, the use of a clock may also regulate or delay the operation of the fastest sub-circuits within an integrated circuit. This, in turn, may not allow the faster sub-circuits within the integrated circuit to take advantage of time-borrowing (e.g., process input signals as soon as the input signals are provided to the sub-circuit). Furthermore, a clock may also be used to hold a sub-circuit in a precharge state until the sub-circuit is allowed to process information. Thus, the use of a clock may result in a circuit being in a precharge condition during a portion of the clock cycle. This may result in the integrated circuit consuming more current, which is generally not desirable in low-power applications. Thus, there is a continuing need for better ways to improve the performance of an integrated circuit while reducing its power consumption.
REFERENCES:
patent: 5355035 (1994-10-01), Vora et al.
patent: 5391938 (1995-02-01), Hatsuda
patent: 5486785 (1996-01-01), Blankenship
patent: 5568069 (1996-10-01), Chow
patent: 5898321 (1999-04-01), Ilkbahar et al.
patent: 6246265 (2001-06-01), Ogawa
patent: 6310509 (2001-10-01), Davenport et al.
Texas Instruments Data Sheet, “SN54180, SN74180 9-Bit Odd/Even Parity Generators/Checkers”, Dec. 1972, pp. 2-597 through 2-599.*
J.B. Kuo, J.H. Lou, “Low-Voltage CMOS VLSI Circuits,” pp. 163-234, John Wiley & Sons, Inc., New York. Date Missing.
J.P. Uyemura, “Circuit Design for CMOS VLSI”, pp. 166-206, Kluwer Academic Publishers, Boston. Date Missing.
Clark Lawrence T.
Wagner Kimberley E.
Chang Daniel
Intel Corporation
Seddon Kenneth M.
LandOfFree
Apparatus and circuit having reduced leakage current and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and circuit having reduced leakage current and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and circuit having reduced leakage current and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3100480