Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2000-06-29
2003-11-11
Bragdon, Reginald G. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C710S068000, C712S210000
Reexamination Certificate
active
06647462
ABSTRACT:
FIELD OF THE INVENTION
The invention concerns an apparatus and a method for providing decoded information and especially an apparatus having a cache for storing and providing decoded information to an information recipient.
BACKGROUND OF THE INVENTION
As used herein, the word “information” is intended to include any type of data or instructions or both. As used herein, the words encode, encrypt, encipher, compressed and the words decode, decrypt, decipher and decompress, and related is forms, are intended to include any form of coding for any purpose, including, but not limited to obscuring meaning, compaction or compression to occupy less space or transmission time, or any other information technique. The words encode, encipher, encrypt, compress are intended to have the same meaning, and likewise for their inverse forms, e.g., decode, decipher, decrypt and decompress. For convenience of explanation, and without limiting the meaning of the terms “information” and “coded” as set above, the terms “instruction” and “coded” are used in the pages below.
There is a need to store instructions in coded form. This can arise because of a desire to make the instructions opaque to unintended users or to conserve memory space through some means of redundancy elimination or compaction coding or for other reason.
Storing instructions in coded form causes several problems, among which is the need to decode the instruction that is retrieved from the memory. When coded instruction must be refetched there is a need to decode it again, thereby causing a waste of time and degradation of apparatus performances.
In many computer apparatuses, these problems are more acute when a change of flow occurs. When a change of flow occurs instruction has to be fetched from the memory and decoded before being provided to a CPU of the computer apparatus.
A change of flow can occur for various reasons, such as an execution of an instruction that involves conditional or unconditional branching. A branch target instruction is the instruction that is fetched by the CPU when executing a branch instruction. The address of the branch target instruction is known as ‘branch target address’ and is a part of any branch instruction. In some instructions, such as the Isync instruction of the PowerPC microprocessor, the branch target address is predetermined, it is driven from the opcode alone.
This problem also arises when a branch prediction is erroneous. In such a case there is a need to refetch the instruction that follow the branch instruction.
The mentioned above waste of time and degradation of apparatus performances are especially acute in computer apparatuses that are supposed to handle very frequent changes of flow.
Another problem related to the storage of instructions in coded form is that the length of the instructions vary in a manner that the coded instructions are not aligned. Furthermore, a single coded instruction can be stored in a portion of a memory word or even in more than a single memory word.
There is a need to allow frequent changes of flow with minimum penalty. There is an ongoing need for improved computers and computer memory organization and operating methods which reduce or eliminate these and other well known limitations of the prior art.
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patent: 5870576 (1999-02-01), Faraboschi et al.
patent: 5915262 (1999-06-01), Bridgers et al.
patent: 6237083 (2001-05-01), Favor
patent: 6367001 (2002-04-01), Witt
patent: 6381689 (2002-04-01), Witt et al.
patent: 0957428 (1999-11-01), None
Dor Amit
Miretsky Alexander
Natan Rami
Sukonik Vitaly
Bragdon Reginald G.
Motorola Inc.
Vital Pierre M.
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