Antireflection layer and process for lithographically structurin

Details Antireflection layer and process for lithographically structurin Antireflection layer and process for lithographically structurin

1995-03-20

1998-05-05

Breneman, R. Bruce

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438724, 438952, 430316, 430950, H01L 21302

Patent

active

057473889

ABSTRACT:
A thick layer formed of aSi or aSi/aSiN is used as an antireflection layer (3) in the lithographic structuring of layers (2) on a semiconductor substrate (1). A reflection suppression is based on absorption in the aSi layer and on interference in the aSiN layer. An optical decoupling of the background is achieved, with the result that the antireflection layer can be used universally.

REFERENCES:
patent: 4541892 (1985-09-01), Jeuch
patent: 4563367 (1986-01-01), Sherman
patent: 4714668 (1987-12-01), Uneno et al.
patent: 5141564 (1992-08-01), Chen et al.
patent: 5254488 (1993-10-01), Haller
patent: 5258608 (1993-11-01), Uchiya
patent: 5360510 (1994-11-01), Kadomura
patent: 5398133 (1995-03-01), Tsai et al.
patent: 5418019 (1995-05-01), Chen et al.
Patent Abstract of Japan No. JP 1015951 (Masato) May 10, 1989.
8226 Microelectronic Eng. Publ. 21(1993)Apr., No.1/4, pp. 51-56, "Reduction of Linewidth Variation for the . . . ".

Affiliated with

Also associated with

Rating

Antireflection layer and process for lithographically structurin does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Antireflection layer and process for lithographically structurin, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Antireflection layer and process for lithographically structurin will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-53955