Antifuse structure and method of fabrication

Fishing – trapping – and vermin destroying

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437 51, 437 52, 437192, 437922, 148DIG55, H01L 21283

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active

053957970

ABSTRACT:
An antifuse structure (20) and method of fabrication are provided. A first conductive layer (A) is etched according to a first mask (62a) having a first pattern and according to a second mask (64a) having a second pattern. A first insulative layer (30) is disposed over the first conductive layer (A) and etched according to a third mask (40a) having a third pattern to expose at least one section of the first conductive layer (A). A second insulative layer (26) is disposed adjacent at least one exposed section of the first conductive layer (A). A second conductive layer (1) is disposed over the second insulative layer (26) so that the antifuse structure (20) includes at least one antifuse region (A1) where a section of the second insulative layer (26) is adjacent the first (A) and second (1) conductive layers. The antifuse region (A1) has a sublithographic vertical dimension (t) according to a thickness of the first conductive layer (A). Further, the antifuse region (A1) has a sublithographic horizontal dimension (L) according to an overlap between the first (62a) and second (64a) masks.

REFERENCES:
patent: 5059555 (1991-10-01), Iranmanesh et al.
patent: 5166556 (1992-11-01), Hsu et al.
patent: 5171715 (1992-12-01), Husher et al.
patent: 5196724 (1993-03-01), Gordon et al.
Kueing-Long Chen, David K. Y. Liu, George Misium, W. Milton Gosney, Shoue-Jen Wang, Janet Camp and Howard Tigelaar, "A Sublithographic Antifuse Structure for Field-Programmable Gate Array Applications", IEEE Electron Device Letters, vol. 13, No. 1, Jan. 1992, pp. 53-55.

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