Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate
2001-09-25
2003-04-08
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having fuse element
C365S096000, C365S200000
Reexamination Certificate
active
06545928
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to semiconductor integrated circuits. More particularly, it pertains to enhancing the process of programming antifuse circuitry so that less time is required to manufacture an integrated circuit, such as a memory device.
BACKGROUND OF THE INVENTION
Semiconductor manufacturers generally incorporate antifuse circuitry into an integrated circuit, such as a memory device. The antifuse circuitry, like read-only memory, can be programmed to uniquely identify the memory device or provide other information about the memory device. Identifying information may include a serial number, various types of circuit components that are on the memory device, and the manufacturing date and time. If the memory device is returned to the manufacturer for various reasons, the manufacturer can extract these pieces of information to improve its manufacturing processes. Another use for the antifuse circuitry is for repairing a memory device that has defective memory cells. The antifuse circuitry can be programmed to remap addresses of these defective memory cells to functional memory cells of the memory device. In this way, the antifuse circuitry helps to salvage defective memory devices.
Antifuses are fabricated with a structure similar to that of a capacitor in which two conductive terminals are separated by a dielectric layer. In the unprogrammed state in which the antifuse is manufactured, a high resistance exists between the two conductive terminals. To transition the unprogrammed state of the antifuse to a programmed state, a large programming voltage is applied across the two conductive terminals of the antifuse to break down the interposed dielectric layer. When the dielectric layer is broken down, a short is created to electrically link the two conductive terminals of the antifuse so that current can flow between the two conductive terminals.
This programming current, in certain circumstances, may be too large and can create a problem in the programming of other antifuses.
FIG. 1
is a circuit diagram of a conventional antifuse circuitry
100
in which this problem is further explained. An antifuse
102
has a first terminal coupled to a node
108
and a second terminal coupled to a node
110
. Also coupled to the node
110
is a source of an n-channel transistor
104
; its gate is coupled to a source of positively pumped voltage, and its drain is coupled to a node
112
. A source of another nchannel transistor
106
is coupled to the node
112
; the gate of this transistor is coupled to a node
116
, and its drain is coupled to a node
114
.
When an antifuse
102
is to be programmed, three signals are provided to the antifuse circuitry
100
. A signal CGND at a high voltage level, such as about
10
volts, is provided at the node
108
. Another signal to turn ON the n-channel transistor
106
is a signal DQ* (or the complement of a signal DQ) provided at the node
116
at a high voltage level. A third signal, which is at ground, is an ADDRESS or FA (FUSE ADDRESS) signal, and it is provided at the node
114
. When these three signals are provided to the antifuse circuitry
100
, the antifuse
102
changes its highly resistive state to a short, and thereby, this change in state denotes a desired bit of information.
More specifically, the large programming voltage of the CGND signal breaks down the dielectric layer of the antifuse
102
, and hence, creates a short between the two conductive terminals of the antifuse
102
. Both the n-channel transistors
104
and
106
are turned ON because their gates are coupled to the high voltage signals. Therefore, a conductive path is set up for a programming current to flow through the antifuse
102
to reach ground at the source of the ADDRESS signal. However, if this programming current is too large, it may depress the programming voltage of the CGND so that other antifuses may be prevented from being programmed at the same time as the antifuse
102
. To fix this, one may shut down the programming process, change the address to point to the next antifuse to be programmed, and turn ON the programming process again. The problem with this approach is that it lengthens the programming time of antifuses, which delays the manufacturing process and results in costlier products.
One technique to solve this problem so that the overall programming time is minimized is discussed by Sher et al. in U.S. Pat. No. 5,668,751. Sher et al. describe a circuit
101
shown in
FIG. 2
that includes an antifuse
103
having a first terminal coupled to a node
113
from which a programming voltage signal is provided and a second terminal coupled to a node
117
. Also coupled to the node
117
is a first terminal of a switch
105
. A second terminal of the switch
105
is coupled to a node
119
. A current monitor
107
to monitor current flowing through the antifuse
103
is coupled to the node
119
at one of its three terminals; its second terminal is coupled to ground
115
and its third terminal is coupled to a comparison circuit
109
via a node
121
. The result of the comparison is sent to a delay circuit
111
by the comparison circuit
109
via a node
123
. The delay circuit
111
controls the state of the switch
105
by sending over the node
125
a control signal to turn the switch
105
ON or OFF.
When the antifuse
103
is to be programmed, the switch
105
is ON and a high voltage signal is provided at the node
113
to break down the high-resistance dielectric of the antifuse
103
. More current will flow as the dielectric becomes less resistive. This current is monitored by the current monitor
107
, and the monitored current is communicated to the comparison circuit
109
via the node
121
. When the monitored current reaches a trigger level, the comparison circuit
109
allows the delay circuit
111
to initiate a delay period, which is preprogrammed to reflect the time required to break down the dielectric to obtain a desired level of conductance. At the end of this delay period, the delay circuit
111
turns OFF the switch
105
to thereby interrupt the current through the antifuse
103
.
Thus, the circuit
101
of Sher et al. minimizes the programming time by focusing on limiting the time spent to program each antifuse through the use of a customized delay period. However, unlike the present invention, Sher et al. do not seem to recognize the need to program multiple fuses contemporaneously. To program multiple fuses using the circuit
101
of Sher et al. would require duplicating a number of components discussed above. This may increase both cost and complexity in manufacturing. Thus, there is a need for devices and methods to limit the current during programming of an antifuse so that other antifuses may be programmed at the same time without increasing cost and complexity.
SUMMARY OF THE INVENTION
An illustrative aspect of the present invention includes a circuit and a method for limiting current drawn by an antifuse during programming. A voltage, generated from current that indicates whether the antifuse is programmed, is detected. This detected voltage enables an inhibitor to create an open circuit between a programming voltage supply and ground to inhibit the antifuse from thereafter drawing a large amount of current. The act of inhibiting is contemporaneously executed without waiting for a predetermined period of time to elapse by a delaying circuit.
REFERENCES:
patent: 5418738 (1995-05-01), Abadeer et al.
patent: 5668751 (1997-09-01), Sher et al.
patent: 5680360 (1997-10-01), Pilling et al.
patent: 6016264 (2000-01-01), Lin
patent: 6128241 (2000-10-01), Choi
Dorsey & Whitney LLP
Micro)n Technology, Inc.
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