Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Non-single crystal – or recrystallized – active junction...
Reexamination Certificate
2000-12-18
2003-08-05
Coleman, William David (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Non-single crystal, or recrystallized, active junction...
C257S530000
Reexamination Certificate
active
06603142
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to antifuses. More particularly, the present invention relates to metal-to-metal antifuses incorporating improved barrier metal layers.
2. The Prior Art
Antifuses are known in the art and find applications in such devices as field programmable gate array (FPGA) integrated circuits in which they are used to program logic module functions and wiring interconnections. An antifuse comprises a pair of conductors spaced apart by an antifuse material which may include a single layer or may include multiple layers.
An antifuse initially exhibits an extremely high resistance between the pair of conductors. An antifuse is programmed by placing a programming potential across the pair of conductors to disrupt the antifuse material and create at least one conductive filament formed from the material from one or both electrodes to provide a low-resistance path between the pair of conductors.
Antifuses are characterized as either substrate antifuses, in which the lower conductor comprises a doped region in a semiconductor substrate and the upper conductor comprises a material such as a metal or polysilicon layer, or metal-to-metal antifuses, in which both the conductors comprise metal layers disposed above the surface of the semiconductor substrate. Substrate antifuses typically employ one or more silicon dioxide and silicon nitride layers as the antifuse material. Metal-to-metal antifuses typically employ a layer of amorphous silicon bounded by TiN diffusion barrier layers as the antifuse material.
Metal-to-metal antifuses have several advantages. They exhibit a lower on resistance than do substrate antifuses. The lower resistance permits higher speed operation of devices that employ them. In addition, because metal-to-metal antifuses are disposed in metal layers lying above the semiconductor substrate, they do not consume any substrate area and can be formed directly above active devices in the substrate, providing substantial savings in chip area.
Presently-employed metal-to-metal antifuses are subject to certain disadvantages which cause serious design constraints. When employed in circuits where substantial currents flow through the metal-to-metal antifuse during its use after programming, the antifuse can “switch off” due to thermally activated processes such as stress voiding and metal electromigration. As a result of this limitation, metal-to-metal antifuses cannot easily be employed in higher current DC paths, such as in Vcc and Vss lines. In addition, care must be taken to design signal paths that do not exceed an upper limit of peak AC current flow through the programmed metal-to-metal antifuse.
BRIEF DESCRIPTION OF THE INVENTION
According to a first aspect of the present invention, a metal-to-metal antifuse disposed above and insulated from a semiconductor substrate comprises a first metal layer disposed above and insulated from the semiconductor substrate. A layer of antifuse material is disposed over and in electrical contact with the first metal layer. A second metal layer is disposed over and in electrical contact with the layer of antifuse material. At least one barrier layer comprising a layer of TaN is disposed between the layer of antifuse material and one of the first and second metal layers.
According to a second aspect of the present invention, a method for forming a metal-to-metal antifuse disposed above and insulated from a semiconductor substrate, comprises forming a first metal layer disposed above and insulated from the semiconductor substrate, forming a layer of antifuse material over and in electrical contact with the first metal layer, forming a second metal layer over and in electrical contact with the layer of antifuse material, and forming at least one barrier layer comprising a layer of TaN between the layer of antifuse material and one of the first and second metal layers.
REFERENCES:
patent: 4899205 (1990-02-01), Hamdy et al.
patent: 5008855 (1991-04-01), Eltoukhy et al.
patent: 5126282 (1992-06-01), Chiang et al.
patent: 5272101 (1993-12-01), Forouhi et al.
patent: 5272388 (1993-12-01), Bakker
patent: 5308795 (1994-05-01), Hawley et al.
patent: 5614756 (1997-03-01), Forouhi et al.
patent: 5705849 (1998-01-01), Zheng et al.
patent: 5741720 (1998-04-01), Hawley et al.
patent: 5920109 (1999-07-01), Hawley et al.
patent: 5962910 (1999-10-01), Hawley et al.
patent: 6107165 (2000-08-01), Jain et al.
patent: 6124194 (2000-09-01), Shao et al.
Lambertson Roy
Ranaweera Jeewika
Actel Corporation
Coleman William David
Sierra Patent Group Ltd.
LandOfFree
Antifuse incorporating tantalum nitride barrier layer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Antifuse incorporating tantalum nitride barrier layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Antifuse incorporating tantalum nitride barrier layer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3087037