Antifuse development using &agr;-C:H,N,F thin films

Details Antifuse development using &agr;-C:H,N,F thin films Antifuse development using &agr;-C:H,N,F thin films

2000-09-05

2001-11-13

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S131000, C438S467000, C438S482000

Reexamination Certificate

active

06316346

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to integrated circuit antifuse structures.
The first commercial antifuse based Field Programmable Gate Array (FPGA) employed an oxide
itride/oxide (ONO) dielectric sandwiched between heavily doped polysilicon and a heavily doped diffusion in single crystal silicon. Because the antifuse is constructed on substrate next to the logic modules, this type of antifuse takes up valuable silicon area. In addition, because of reliability constraints, the programming voltage of this dielectric could not be scaled to less than about 14 volts. This causes an increasing problem as supply voltages are scaled.
The next commercial antifuse based FPGA employed an amorphous silicon antifuse dielectric sandwiched between two of the interconnect layers overlying the logic modules. This significantly reduced the size of the antifuse chip because antifuses could be constructed above rather than alongside the logic modules. In addition, the programming voltage was reduced to about 10 volts which helps with scaling supply voltages. The limitations of this dielectric are that (1) the programming voltage cannot be scaled below about 8 volts because of a rapid increase in off state leakage as the amorphous silicon thickness is reduced, and (2) a programming current of about 20 mA is required to stabilize the conductive filament. With amorphous silicon, insufficient programming current can result in a filament that will switch to a high resistance state during use. The amorphous carbon and nitrided amorphous carbon dielectrics described herein overcome many of these limitations. The programming voltage of the amorphous carbon dielectric antifuses can be scaled to less than 5 volts while still maintaining picoamp leakage current in the off state. The resistance of the programmed filament can be reduced to less than 100 ohms with 5 mA of programming current. Furthermore, the filament exhibits none of the resistance instability problems seen with amorphous silicon.
The present application discloses a metal-to-metal antifuse with an amorphous carbon dielectric which provides a very high resistance off state and can be programmed at voltages compatible with deep submicron devices. Furthermore, the programmed filament achieves low resistance with low programming current while maintaining a high level of stability.
One limitation of the hydrogenated amorphous carbon films is that they begin to evolve hydrogen and convert to low resistance graphite at temperatures above 250° C. This imposes a constraint on the maximum temperature that can be used in post antifuse processing of the integrated circuits. Either nitrogen and/or fluorine doping of hydrogenated films or the deposition of low hydrogen content amorphous carbon films stabilizes the films to temperatures exceeding 400° C. These temperatures are commonly used in back-end semiconductor processing.
The antifuse structure can be constructed between two of the interconnect layers overlying the logic modules in an FPGA, permitting a very compact layout. The antifuse structure consists of the bottom interconnect metal, the amorphous carbon dielectric, and the top interconnect metal. In between the interconnect metal layers and the amorphous carbon dielectric a layer of barrier metal such as TiW, Ti, or TiN, may be used.


REFERENCES:
patent: 4630355 (1986-12-01), Johnson
patent: 5493147 (1996-02-01), Holzworth et al.
patent: 5825072 (1998-10-01), Yen et al.
patent: 5989943 (1999-11-01), Whitten et al.

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