Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate
2002-01-09
2003-09-23
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having fuse element
C365S096000, C365S189050, C365S200000
Reexamination Certificate
active
06625080
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and in particular the present invention relates to antifuse detection circuits.
BACKGROUND OF THE INVENTION
Programmable devices are commonly used for changing a circuit after it has been fabricated. One application of programmable devices is in the repair of integrated circuit memories. Integrated circuit memories are often fabricated with several redundant elements (rows or columns) of memory cells. Each redundant element has an associated comparison module which is formed by an array of programmable devices and which is capable of receiving a multi-bit address. The programmable devices of the array are selectively programmed to respond to a specific address as necessary to reroute memory addresses for replacing a redundant element for a failed memory element.
One type of programmable device that is commonly used for these applications is the anti-fuse. In its unprogrammed condition, the anti-fuse functions as a capacitor and presents a very high resistance on the order of 10 Megohms. To program an antifuse, its connections are shorted together providing a relatively low resistance path through the anti-fuse, typically presenting a resistance of about 200 to 500 ohms. Typically, a detection circuit is used to determine the condition of an anti-fuse. The detection circuit includes a pull-up transistor that is connected in series with the anti-fuse between the Vcc rail and the ground rail of the detection circuit. A voltage level detecting circuit connects the ungrounded terminal of the anti-fuse at a detection node to the output of the detection circuit. For an unblown condition for the anti-fuse, a voltage at approximately Vcc is provided at the detection node. For a blown condition for the anti-fuse, the shorted anti-fuse connects ground to the input of the level detecting circuit. A latch arrangement, triggered by the voltage level detecting circuit, is provided to isolate the detection node and the blown anti-fuse from the Vcc rail for the blown condition for the anti-fuse.
In programming an anti-fuse, the anti-fuse may not blow clean. In such case, the anti-fuse presents a relatively high resistance which can be on the order of 400 K ohms. Accordingly, a partially blown anti-fuse forms a voltage divider in combination with the pull-up transistor so that rather than being at ground, the voltage provided at the detection node will trip the level detecting circuit, so that the detection circuit will produce an erroneous output.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a detection circuit which can identify a programmed device, in particular a high resistance antifuse.
SUMMARY OF THE INVENTION
The above mentioned problems with detection circuits and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A detection circuit is described which uses multiple programmable devices and a latch to detect a programmed device.
An antifuse detection circuit is described which uses a latching circuit and two antifuses. The antifuses are coupled between the latch circuit and ground. The latching circuit described is a differential circuit which can detect which one of the two antifuses has been programmed. The circuit accurately detects an antifuse which has a relatively high resistance after being programmed.
In particular, the present invention describes an antifuse detection circuit comprising a latch circuit, and a plurality of antifuses coupled between the latch circuit and a common reference voltage.
In another embodiment, an antifuse detection circuit is described which comprises first and second antifuses. Each antifuse having a first node connected to a common reference voltage, and a second node connected to a latch circuit. The latch circuit comprises first and second cross-coupled p-channel transistors. A drain of the first and second p-channel transistors is connected to a second reference voltage. A source of the first p-channel transistor is coupled to a gate of the second p-channel transistor, and a source of the second p-channel transistor is coupled to a gate of the first p-channel transistor. The first antifuse is coupled to the source of the first p-channel transistor, and the second antifuse is coupled to the source of the second p-channel transistor.
In yet another embodiment, a memory device is described which comprises an array of memory cells, and control circuitry. The control circuitry comprises a latch circuit having cross-coupled transistors and a plurality of antifuses coupled between the latch circuit and a common reference voltage.
A method is described for detecting a programed antifuse. The method comprises the steps of programming a first antifuse to create a conductive path between first and second conductive plates, coupling the first conductive plate to a first reference voltage, and coupling the second conductive plate to a latch circuit. The method further includes the steps of coupling a first conductive plate of an un-programmed second antifuse to the first reference voltage, coupling a second conductive plate of the second antifuse to the latch circuit, and activating the latch circuit.
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Casper Stephen L.
Martin Chris G.
Micro)n Technology, Inc.
Nguyen Viet Q.
Schwegman Lundberg Woessner & Kluth P.A.
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