Antifuse circuitry for post-package DRAM repair

Details Antifuse circuitry for post-package DRAM repair Antifuse circuitry for post-package DRAM repair

2000-01-10

2001-05-29

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having fuse element

C365S200000, C365S096000, C257S050000, C257S530000

Reexamination Certificate

active

06240033

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to an electrically programmable integrated circuit and an associated device structure for implementing a nonvolatile memory; and, more particularly, to anti-fuse circuitry, which is capable of effectively providing a post-package repair with electrically programmable anti-fuses.
DESCRIPTION OF THE PRIOR ART
A laser trimmed poly-silicon fuse structure is widely used in a programmable repair of a dynamic random access memory (DRAM) chip which is typically performed at a wafer level, typically, before a burn-in test. In a laser trimmed repair method employing the laser trimmed poly-silicon fuse structure, defective memory cells are identified by a wafer probe testing process. The poly-silicon fuse structure is then programmed by using a laser trimming technique to activate an address decoding of redundant memory cells in order to repair the DRAM chip. While the laser trimmed fuse structure is compact and reliable, the laser trimmed repair method can only be efficiently performed at the wafer level. As a result, it may preclude the ability for repairing any defective memory cell, which is found after a packaging process and generally occurs during the burn-in test.
On the other hand, with an electrically programmable nonvolatile memory, many types of post package failures can be repaired resulting in a significant yield improvement of a high density DRAM.
An anti-fuse structure and associated circuitry suitable for use in integrated circuits are generally incorporated in a nonvolatile memory device. It is expected to be particularly useful for an electrically programmable repair technique of a DRAM using a redundant memory capacity. Specifically, through the addition of special test modes, it is possible to implement this functionality without any alteration of the existing product pin-out specifications.
On the other hand, in addition to its uses in DRAM manufacture, it may be envisioned that this functionality can also be effectively utilized in the field or by end users as a part of a test-and-repair procedure. Similarly, it is also possible to program other useful and unique nonvolatile data into the DRAM component such as encryption keys, serial numbers, manufacture dates and other quality tracking identification.
A basic anti-fuse element is generally a resistive fuse component which has a very high resistance (>100 Mohm) in its initial unprogrammed state and, after an appropriate programming operation, will have a significantly lower resistance (<10 Kohm). The anti-fuse element is typically composed of a very thin dielectric material such as silicon dioxide, silicon nitride, tantalum oxide or a sandwich combination of dielectrics such as ONO (silicon dioxide-silicon nitride-silicon dioxide) between two conductors. The anti-fuse is programmed by applying an appropriate programming voltage under sufficient current flow through terminals of the anti-fuse for a sufficient time to cause the resistance of the anti-fuse to permanently change from high to low.
The programming voltage is typically larger in magnitude than a normal operating voltage so that the programming voltage may cause damage and reduce the reliability of associated neighboring devices and peripheral circuitry, which are improperly isolated. In particular, the peripheral circuitry for providing the programming voltage and for reading an anti-fuse resistance will typically be directly attached to the anti-fuse element to thereby be subjected to potential damage.
The integrity of the anti-fuse in both of its initial unprogrammed and programmed states may be adversely affected by several factors. For example, an extended exposure at elevated temperatures or application of a continuous current or voltage bias across the anti-fuse element may alter the properties of the thin dielectric resulting in an increase or decrease in the anti-fuse resistivity and potentially causing an error or degraded performance thereof. When programming a single anti-fuse element, an internally or externally generated programming voltage (or current) signal, Vhv (or Ihv), is applied across terminals of the anti-fuse element for a sufficient time. However, when a plurality of anti-fuse elements is used such as in a multiplexed array, non-selected anti-fuse elements may be subjected to unintentional programming signals resulting in an accidental change of conductivity of the thin dielectrics.
The reliable programming and reading of the anti-fuses requires several important key components.
First, an appropriate programming voltage or current signal must be generated internally or supplied externally. Specifically, an internal high voltage for the anti-fuse programming requires a careful isolation and biasing of device structures such as PN junctions and gate dielectrics, in order to insure that they are not subjected to large voltage differences. The large voltage differences may cause a premature breakdown, a reduced reliability, an excessive leakage current, a field oxide inversion, latch-up or failure. Similarly, if the programming voltage is provided externally, there must be a method of supplying this voltage without interference from normal electro-static discharge(ESD) circuitry typically used on the integrated circuit output pads and/or pins.
Second, there should be a method to address-select and program individual anti-fuses which also requires further manipulation of a programming signal.
Third, an appropriate method for sensing or reading the state of the anti-fuse is required. The anti-fuse state is typically read upon device activation or immediately after powered up. In order to reduce a risk of an anti-fuse failure due to a continuous read operation and to improve a read access speed to the anti-fuse information, a volatile memory should be provided with appropriate circuitry which can effectively provide a proper sense/latch operation of the anti-fuse state in a wide range of operating conditions.
However, up to date, there is no circuitry for effectively implementing the above three requirements.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide an anti-fuse circuit, for use in an anti-fuse based random access memory (RAM), which is capable of proving improved yield, reliability and functionality of a RAM, specifically a synchronous DRAM (SDRAM).
A schematic block of this invention is simply illustrated as shown in FIG.
1
. The present invention includes three sub-blocks: a multiplexer having inputs of control signals and addresses and yielding the activation of a programming signal and program addresses (sub-block
10
); a programming voltage generator consisting of an oscillator and a charge pump (sub-block
20
); and an anti-fuse unit circuit for the program/read of anti-fuse states (sub-block
30
).
First, for an anti-fuse program at a special test mode, the sub-block
10
having inputs of control signals and addresses activates the programming voltage generator and makes a special or program address for the selection of an anti-fuse unit circuit. In a normal mode, the sub-block
10
and the sub-block
20
remain at an inactive state. In the sub-block
30
, the program address and the programming voltage signal from the programming voltage generator serve to switch the terminal of the anti-fuse up to a programming voltage level when the anti-fuse is selected for programming of anti-fuse elements.
In accordance with one embodiment of the present invention, in the sub-block, an internal voltage generator comprises several specific-devised elements for enduring a negative voltage or a high voltage. As shown in
FIG. 2
, two types of voltage generators are illustrated with diodes and capacitors used for a special purpose. The capacitors (C
2
~C
6
) coupled to a high voltage generator and each diode are made of poly and metal layers, which are formed as layer-by-layer stacked arrays (named as “finger-shaped stacked-array capacitor”). They have a bigger capacitance (6~7 times) than that of a planar metal capacitor at the same area and

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