Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate
1998-11-23
2003-04-08
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having fuse element
C365S096000, C365S189050, C365S149000
Reexamination Certificate
active
06545926
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an antifuse address detecting circuit and a semiconductor integrated circuit device, and particularly relates to a structure which uses antifuses and is programmable by applying a high voltage thereto.
2. Description of the Background Art
A semiconductor integrated circuit device provided with memory cells which are arranged in rows and columns to form an array is also provided with a spare row line and a spare column line, which will be also referred to as “redundant lines” hereinafter. Owing to provision of a redundant structure, a defective memory cell or a defective line is repaired by substituting the redundant line for the defective memory cell or line. Provision of the redundant structure improves a rate of acceptable chips on a wafer.
This structure requires an internal circuit, in which a defective address is programmed in advance. In a practical operation, the internal circuit monitors the row and column addresses which are actually input, and can perform substitution of the spare line when it detects that a defective address is input.
For example, Journal of Solid State Circuit Vol. SC-18 (1983), pp. 441-446 (which will be referred to as a “reference
1
” hereinafter) has disclosed a fuse-bank address detecting circuit, which is an example of the above internal circuit.
An example of a structure of a conventional fuse-bank address detecting circuit
800
disclosed in the reference
1
will be described below with reference to FIG.
23
. The conventional fuse-bank address detecting circuit
800
shown in
FIG. 23
includes a plurality of fuses F
11
, F
12
, . . . , Fm
1
and Fm
2
as well as a plurality of transistors T
11
, T
12
, . . . , Tm
1
, Tm
2
and Tx. Fuses F
11
-Fm
2
which are program elements are connected to a common node Z. A fuse corresponding to a defective address is blown in advance. Thereby, the defective address is programmed (stored). A transistor Tx charges and thereby initializes common node Z in response to a precharge signal PR.
Transistors T
11
-Tm
2
are arranged correspondingly to fuses F
11
-Fm
2
, respectively. Transistors T
11
, T
12
, . . . , Tm
1
and Tm
2
receive address signals a
1
, /a
1
, . . . , am and/am on their gates, respectively. A signal (inactivating signal fDA) on common node Z changes depending on matching and mismatching between the input address signal and the programmed defective address. A decoder (not shown) receiving this signal selects the redundant line instead of the defective line.
However, the conventional fuse-bank address detecting circuit
800
shown in
FIG. 23
requires an expensive laser cutter device for blowing off the fuse. Also, a process load for blowing off the fuse is large, and further a variation occurs in accuracy of blowing.
In contrast to the foregoing, U.S. Pat. No. 5,631,862 (May 20, 1997), which will be referred to as a “reference
2
” hereinafter, has disclosed a structure of an antifuse address detecting circuit which does not use a fuse.
An antifuse program circuit
900
which is included in the conventional antifuse address detecting circuit disclosed in the reference
2
will be described below with reference to FIG.
24
.
Antifuse program circuit
900
shown in
FIG. 24
includes PMOS transistors P
8
, P
9
and P
10
, NMOS transistors N
11
, N
12
, N
13
, N
14
and N
16
, an inverter circuit
917
and an antifuse
901
.
Antifuse
901
has a structure of a capacity type, and usually functions as an open circuit. However, by applying a high voltage thereto and thereby blowing the capacity type structure, it forms a conductive path having a resistance of about several kilohms.
NMOS transistor N
16
and antifuse
901
are connected in series between nodes VCON and CGND. Node CGND is set to a level of a ground potential GND in a normal mode, and is supplied with a high voltage of 10 V or more when antifuse
901
is blown (i.e., in an address program mode).
NMOS transistor N
16
operates such that a voltage higher than a breakdown voltage of a gate oxide film may not be applied across the sources and gates, or drains and gates of NMOS transistors N
11
, N
12
and N
13
when a high voltage of 10 V or more is applied to node CGND.
NMOS transistors N
12
, N
13
and N
14
are connected in series between the ground potentials. NMOS transistor N
12
receives on its gate electrode a reset signal RST. Reset signal RST is active and at H-level when it is initially set. NMOS transistor N
13
receives on its gate electrode an address signal ADDR.
NMOS transistor N
14
receives on its gate electrode a signal FR which is an output of inverter circuit
917
(i.e., an output of this circuit). Signal FR is an input signal of an address comparing circuit (not shown), which is formed of an NOR logic gate or an NAND logic gate, and performs comparison of address signal ADDR. NMOS transistor N
14
may be turned off with signal FR to interrupt a path of current, which tends to flow toward the ground potential via nodes VCOM and NMOS transistors N
13
and N
14
when blowing antifuse
901
.
PMOS transistors P
8
and P
9
are connected between an internal power supply potential VCC and a node W. PMOS transistor P
8
receives on its gate electrode a signal T(RAS). PMOS transistor P
9
receives signal FR on its gate electrode.
PMOS transistor P
10
and NMOS transistor N
11
are connected in series between nodes W and VCOM. NMOS transistor N
11
receives a signal DVCE on its gate electrode. Signal DVCE is an enable signal of this circuit, and its level is raised to half the internal power supply voltage (Vcc/2) when blowing antifuse
901
or detecting the address. PMOS transistor P
10
has a channel length and a channel width which are determined to provide a channel resistance of about 300 K&OHgr;, and is always on.
NMOS transistor N
11
has a channel length and a channel width which are determined to provide a current drive power exceeding that of PMOS transistor P
10
. Inverter circuit
917
is connected to a connection node between PMOS and NMOS transistors P
10
and N
11
.
In the foregoing circuit, in which programming is performed with the antifuse not requiring laser for blowing, steps for laser blowing can be reduced. Also, an expensive device for blowing is not required.
However, the structure using the antifuse as a program element suffers from such a problem (erroneous programming) that serge (noises) entering an interconnection for voltage application blows an antifuse not requiring programming.
Further, an excessive current flows when the antifuse is blown, and it is necessary to suppress an influence exerted on peripheral elements by the excessive current.
If the antifuse is used as the program element, the antifuse for a defective address must be reliably blown. Even if the blowing is insufficient, a normal operation must be ensured. Further, it is necessary to verify an operation of the antifuse address detecting circuit, and it is also necessary to remove an initial failure in the program elements.
If the above structure is applied to a semiconductor integrated circuit device, it is necessary to reduce the number of circuit elements and therefore a layout area.
SUMMARY OF THE INVENTION
An object of the invention is to provide an antifuse address detecting circuit, overcoming the above problems, which uses an antifuse as a program element, and can suppress an influence, which may be exerted on its peripheral elements by blowing the same.
Another object of the invention is to provide an antifuse address detecting circuit, which uses an antifuse as a program element, and can stably and reliably blow the antifuse.
Still another object of the invention is to provide a semiconductor integrated circuit device, in which an antifuse address detecting circuit programmable by applying a high voltage is used as a redundancy determining circuit, and particularly a semiconductor integrated circuit device which can suppress an influence exerted by the high voltage on a peripheral circuit, and requires a small layout area.
Yet
Hidaka Hideto
Ooishi Tsukasa
Shimano Hiroki
Tomishima Shigeki
Lam David
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
LandOfFree
Antifuse address detecting circuit programmable by applying... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Antifuse address detecting circuit programmable by applying..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Antifuse address detecting circuit programmable by applying... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3090012