Anti-noise and auto-stand-by memory architecture

Details Anti-noise and auto-stand-by memory architecture Anti-noise and auto-stand-by memory architecture

1995-03-29

1998-12-01

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Differential sensing

36518905, 365194, 365206, 3652335, G11C 1300

Patent

active

058448519

ABSTRACT:
Spurious memory readings which may be caused by noise induced by transitions in the output buffers of a fast parallel memory device are prevented by permitting output latches to change state in function of newly extracted data signals by means of an enabling pulse having a preestablished duration and which is generated only after a change of memory address signals has occurred and the new configuration of memory address signals has lasted for a time which is not shorter than the time of propagation of signals through the memory chain. The enabling pulse is generated by employing a detector of transitions occurring in the input circuitry of the memory, a dummy memory chain, a one-shot pulse generator and a resetting pulse generator. The anti-noise network may be exploited also for implementing an auto-stand-by condition at the end of each read cycle, which reduces power consumption and increases speed by simplifying the sensing process.

REFERENCES:
patent: 4800304 (1989-01-01), Takeuchi
patent: 4953130 (1990-08-01), Houston
patent: 4982366 (1991-01-01), Takemae
patent: 5029135 (1991-07-01), Okubo
patent: 5031153 (1991-07-01), Suyama
patent: 5404334 (1995-04-01), Pascucci et al.

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