Anodized polysilicon layer lower capacitor plate of a dram to in

Details Anodized polysilicon layer lower capacitor plate of a dram to in Anodized polysilicon layer lower capacitor plate of a dram to in

1991-05-06

1992-08-11

Larkins, William D.

357 59, H01L 27108

Patent

active

051384116

ABSTRACT:
A DRAM cell having enhanced-capacitance attributable to the use of a textured structured polycrystalline silicon layer storage node capacitor plate. The present invention is particularly applicable to DRAM cells which employ a stacked capacitor design. Such designs generally employ a conductively-doped polycrystalline silicon layer as the storage node, or lower, capacitor plate. A microstructure is formed by anodizing the storage node plate layer in a solution of hydrofluoric acid to produce microstructures resembling elongated depressions in the storage node plate layer. This is followed by the deposition of a thin conformal (typically less than 100 Angstroms) silicon nitride layer which in turn is followed by the deposition of a second polycrystalline silicon (poly) layer, which functions as the capacitor field plate. Since the nitride layer is thin in comparison to the elongated depressions in the storage node plate layer, capacitive area is substantially augmented. Cell capacitance can be increased by more than 1,000 percent using a storage node plate having microstructures thus formed.

REFERENCES:
patent: 4057823 (1977-11-01), Burkhardt et al.
patent: 4801380 (1989-01-01), Parker et al.
patent: 5043780 (1991-08-01), Fazan et al.
patent: 5068199 (1991-11-01), Sandhu
M. I. J. Beale, N. G. Chew, M. J. Uren, A. G. Cullis, and J. D. Benjamin; "Microstructure and Formation Mechanism of Porous Silicon"; Jan. 1, 1985, Appl. Phys. Lett., pp. 86-88.

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