Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1996-10-11
1999-01-12
Fourson, George R.
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438437, 438702, 438692, 438743, H02L 2176
Patent
active
058588582
ABSTRACT:
A method for forming a microelectronic structure includes the steps of forming a mask layer on a substrate, forming a trench in the exposed portion of the substrate, forming a layer of an insulating material which fills the trench and covers the mask layer, and annealing the insulating material at a temperature of at least about 1,150.degree. C. The annealing step can be performed for a period of time of about .5 hours to about 8 hours, and the annealing step can be performed in an inert atmosphere.
REFERENCES:
patent: 5091330 (1992-02-01), Cambou et al.
patent: 5445989 (1995-08-01), Lur et al.
patent: 5492858 (1996-02-01), Bose et al.
Perera et al., Trench Isolation For 0.45 .mu.m Active Pitch and Below, International Electron Devices Meeting, Washington, DC, Dec. 10-13, 1995 IEEE, IEDM 95, 28.1.1-28.1.4, pp. 679-682, 1995.
Lee Han-Sin
Park Moon-han
Park Tai-su
Shin Yu-gyun
Fourson George R.
Samsung Electronics Co,. Ltd.
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