Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1999-05-20
2002-04-23
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S150000, C438S453000, C205S656000, C205S660000, C205S662000, C205S674000
Reexamination Certificate
active
06376285
ABSTRACT:
BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to integrated circuit structures and fabrication methods, and especially to the formation of silicon-on-insulator substrates.
Background: Silicon-on-Insulator Technology
Silicon-on-insulator (SOI) technology is so-called because a thin layer of monocrystalline silicon is formed over an insulator and substrate. The ability to provide a silicon area which is completely surrounded by an insulator can provide, many advantages, including simpler fabrication, reduced capacitive coupling between circuit elements, elimination of latchup, reduced chip size and/or increased packing density and increased circuit speed. Examples of this technology, and some associated problems, are listed below.
a) In bonded wafers, two semiconductor wafers with oxidized surfaces are bonded together to form a buried oxide layer. One silicon surface is thinned to the desired thickness to provide an active area for devices.
b) The process of layer transfer also bonds two wafers and thins one, but uses a wafer having an epitaxial layer of silicon over a layer of porous silicon. After bonding, the first wafer is thinned to the porous silicon layer, which is then removed by etching.
c) Separation by implanted oxygen (SIMOX) creates a buried layer of SiO2 by implanting a high dose of oxygen ions into a silicon-containing wafer, then annealing to react the implanted oxygen with the silicon to form SiO2. An epitaxial layer is sometimes grown on the surface to provide enough depth of crystalline silicon for device fabrication.
d) Full isolation by porous oxidized silicon (FIPOS) uses an epitaxial layer grown on a heavily-doped silicon surface. The heavily-doped layer is selectively converted to porous silicon by anodization through holes in the epitaxial layer, then oxidized to form a buried layer of oxide.
The methods above tend to be expensive, and several consume two wafers to form a substrate. It is difficult to achieve a uniform, minimal thickness of silicon. Other problems include the use of special equipment, defects in the active area, warpage, and stress-induced dislocations.
Further discussion of SOI can be found in Silicon Processing for the VLSI Era, Volume 2, (p 66-83), from which much of the information above was taken, and which is hereby incorporated by reference.
Background: Porous Silicon
Porous silicon is formed by anodic oxidation of a silicon wafer in a solution of hydrofluoric acid and a surfactant, such as methanol. The size of the pores, the porosity, and the thickness of the porous silicon can be controlled; pore size is typically in the range of 10-20 nm, while porosity is typically in the range of 30-70 percent.
Porous silicon has a low dielectric constant and high resistivity, which make it useful for isolation. Since porous silicon has a high surface area for its volume (a few hundred square meters per cubic centimeter), it can be oxidized much more quickly than bulk silicon.
Sato et al., “Epitaxial Growth on Porous Si for a New Bond and Etchback Silicon-on-Insulator”, J
OURNAL OF THE
E
LECTROCHEMICAL
S
OCIETY,
Vol. 142, No. 9, September 1995, discloses a layer transfer method which produces a high-quality epitaxial layer over porous silicon, with greater uniformity of the layers across the wafer. This article is hereby incorporated by reference.
Porous Silicon in Fabrication of Silicon-on-Insulator Substrate
The present application discloses anodizing a silicon wafer to form a porous silicon layer. After partial oxidation of the porous silicon, the surface of the wafer is etched to provide a clean surface for growth and the top layer of silicon is reflowed to provide a continuous silicon surface. An epitaxial layer of silicon is then grown on the porous silicon, followed by a high temperature anneal; during the anneal, the porous silicon collapses in on its voids, forming a layer which is a mixture of silicon and SiO2. Since these two materials are not soluble in each other, they will form separate layers in the high-temperature anneal. This method has the potential to produce a silicon oxide layer with a smooth interface to a high-quality single crystal epitaxial layer, without the warpage and dislocations of the old FIPOS process. Additionally, unlike other silicon-on-insulator methods, this process can potentially produce SOI wafers at close to the same cost as bulk silicon wafers.
Advantages of the disclosed methods and structures includes high quality silicon for active areas.
REFERENCES:
patent: 5810994 (1998-09-01), Lee et al.
patent: 6103598 (2000-08-01), Yamagata et al.
Joyner Keith A.
Swanson Leland S.
Berry Renee R.
Brady III W. James
Garner Jacqueline J.
Nelms David
Telecky , Jr. Frederick J.
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