Annealed poly-silicide etch process

Details Annealed poly-silicide etch process Annealed poly-silicide etch process

1996-02-07

1997-08-05

Quach, T. N.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438593, 438655, H01L 21283, H01L 213205

Patent

active

056542194

ABSTRACT:
A method for forming poly-silicide conductors (CG,GAP) on a semiconductor device (10) includes forming a layer (14) of doped polysilicon over a region of the device (10), then depositing a layer (15) of refractory metal on the layer (14) of doped polysilicon. The layer (14) of doped polysilicon and the layer (15) of refractory metal are then annealed to form a poly-silicide layer (PSL). The poly-silicide layer (PSL) is then etched to form the poly-silicide conductors (CG,GAP).

REFERENCES:
patent: 4504521 (1985-03-01), Widmer et al.
patent: 4608118 (1986-08-01), Curtis et al.
patent: 4816425 (1989-03-01), McPherson
patent: 4992391 (1991-02-01), Wang
patent: 5422311 (1995-06-01), Woo
Wolf, et al., Silicon Processing, vol. 1, 1986, Lattice Press, pp. 384-392.

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