Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-12-18
2001-05-22
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S316000
Reexamination Certificate
active
06236081
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure and a manufacturing method of manufacturing an AND-type non-volatile semiconductor memory device.
2. Description of the Background Art
A cross sectional structure of a memory cell in an AND-type flash memory which is an example of a conventional AND-type non-volatile semiconductor memory device is shown in FIG.
14
. As shown in
FIG. 14
, a memory cell includes a source
3
and a drain
2
, a floating gate
4
, a control gate (word line)
5
, and an insulating film
11
. Source
3
and drain
2
are formed spaced apart on the main surface of a silicon substrate
1
. On each side of these a field oxide film
6
is formed, and below the field oxide film
6
a channel stopper
18
is formed.
On the surfaces of source
3
and drain
2
, an oxide film
17
is formed by thermally oxidizing of these surfaces.
A floating gate
4
includes a lower floating gate
4
b
and an upper floating gate
4
a
. Lower floating gate
4
b
is formed on the main surface of silicon substrate
1
with a tunnel oxide film
8
therebetween. On a side surface of lower floating gate
4
b
, a nitride film
15
and an oxide film sidewall
16
are formed. Nitride film
15
is provided to prevent a bird's beak from forming when oxide film
17
is formed.
Upper floating gate
4
a
extends over lower floating gate
4
b
and oxide film
17
. Consequently, the coupling ratio between floating gate
4
and control gate
5
can be made relatively large, that is, approximately 0.6. On the other hand, the coupling ratio between floating gate
4
and silicon substrate
1
may be kept relatively small, since the area of the base of lower floating gate
4
b
is made small.
The inventor has independently discovered the following problems inherent in the above-mentioned conventional AND-type flash memory. These problems will be described in relation to
FIG. 15
which is an enlarged view of a region
19
in FIG.
14
.
It is difficult to prevent the formation of a bird's beak of oxide film
17
completely even if nitride film
15
is formed on a side surface of lower floating gate
4
b
, and a bird's beak
17
a
forms as shown in FIG.
15
. Since the length of this bird's beak
17
a
may vary, the coupling ratio between silicon substrate
1
and floating gate
4
may also vary. In addition, due to the formation of bird's beak
17
a
, the thickness of tunnel oxide film
8
at each end may vary. Consequently, the erase and program characteristics effected by FN (Fowler-Nordheim) tunneling may vary as well.
Moreover, because the Vth distribution during the program/erase operations expands as a result, it is difficult to detect the narrow band Vth by introducing the multivalued technique. The multivalued technique enables one cell to hold a multi-bit data, and which distinguishes the cell states, typically distinguished between only two states using one reference voltage, into more than two states using a plurality of reference voltages.
Further, because of the presence of bird's beak
17
a
, it is possible that the regions where source/drain regions
3
,
2
and the ends of floating gate
4
overlap and where the electrons pass during the program/erase operations may not be large enough. Thus, the ends of source
3
and drain
2
need to extend farther inward toward floating gate
4
than bird's beak
17
a
. Consequently, the number of thermal diffusion steps increases during the process flow, giving rise to the problem of higher production cost.
Moreover, hydrogen ions and holes are often trapped in nitride film
15
formed on a sidewall of lower floating gate
4
b
. These hydrogen ions and holes may undesirably couple with the electrons in floating gate
4
, causing the electrons in floating gate
4
to be lost. In other words, retention, or the charge-holding characteristic of floating gate
4
into which the electrons are injected, may deteriorate, causing another problem. In addition, the movement of hydrogen ions and holes from nitride film
15
may degrade endurance.
Furthermore, as shown in FIG.
14
and
FIG. 15
, steps exist on the upper surface of oxide film
17
. Specifically, large steps are formed near oxide film sidewall
16
and near field oxide film
6
. Consequently, etch residues may be generated in the steps while upper floating gate
4
a
and control gate
5
are being patterned. In addition, the steps on the surface of oxide film
17
cause a side surface of a developed resist to have a wavelike shape, and the shapes of upper floating gate
4
a
and control gate
5
may vary. In such a case, adverse effects, especially on the erase characteristic, are to be expected.
SUMMARY OF THE INVENTION
The present invention is intended to provide the solutions to the above-mentioned problems. An object of the invention is to prevent a bird's beak from forming directly beneath the peripheral portion of lower floating gate
4
b
, to planarize an interlayer insulation film
10
below upper floating gate
4
a
, and to improve retention and endurance in an AND-type non-volatile semiconductor memory device.
The AND-type non-volatile semiconductor memory device according to the invention is provided with a plurality of memory cells, a first floating gate, an interlayer insulating film, a second floating gate, a control gate, a memory cell array region, and a peripheral circuit region. The plurality of memory cells are formed on the main surface of the semiconductor substrate. The first floating gate is formed on the main surface with a first insulating film of even thickness therebetween. The interlayer insulating film having a flat top surface is formed on the main surface to cover a side surface of the first floating gate by the CVD (Chemical Vapor Deposition) method. The second floating gate extends on the first floating gate and on the interlayer insulating film. The control gate is formed on the second floating gate with a second insulating film therebetween. The memory cells are formed within the memory cell array region. The peripheral circuit for controlling the operation of the memory cells is formed in the peripheral circuit region. The width (D1 in FIG.
4
and
FIG. 5
) of the boundary region located near the boundary between the peripheral circuit region and the memory cell array region is 1 to 1.5 times the distance between first floating gates of the memory cells aligned in the direction in which the control gate extends.
As described above, the interlayer insulating film formed by the CVD method can prevent the generation of bird's beak directly beneath the floating gate. Moreover, the reduction of the thickness of the interlayer insulating film facilitates the planarization of the top surface of the interlayer insulating film. Thus, after patterning the second floating gate and the control gate, the generation of etch residues is also suppressed. In addition, there will be no need to form a nitride film on a side surface of the first floating gate. Further, the inventor has found that, by making the above-mentioned width of the boundary region 1 to 1.5 times the distance between the first floating gates of the memory cells in the direction in which the control gate extends, when the interlayer insulating film is reduced in thickness to planarize its top surface, it is possible to prevent the thickness of the interlayer insulating film at the boundary region from becoming excessively thinner than the thickness of the interlayer insulating film in other parts. Thus, when planarizing the interlayer insulating film, problems such as exposure of the substrate at the boundary region can be avoided.
The top surface of the interlayer insulating film preferably is equal to or higher in level than the top surface of the first floating gate.
Thus, the second floating gate can be prevented from extending toward the substrate, and the generation of unnecessary capacitance between the second floating gate and the substrate is prevented.
The method of manufacturing the AND-type
Chaudhuri Olik
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Pham Hoai
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