Analyzing device for saving semiconductor memory failures

Details Analyzing device for saving semiconductor memory failures Analyzing device for saving semiconductor memory failures

1993-12-01

1995-04-25

Beausoliel, Jr., Robert W.

Excavating

371 103, G06F 1100

Patent

active

054106877

ABSTRACT:
A failure analysis of a semiconductor memory compares data written into and out of each cell of the semiconductor memory. When there is a disagreement, a "1" is written into a failure analysis memory. A disagreement signal is applied as a write command to column and row address fail count memories and is counted by a fail counter. The column address and row address fail count memories receive the column and row addresses, respectively. When the write command is applied to the column and row address fail count memories, the number of defective cells is read out of the memory addresses by a read modify write operation. A 1 is added by column and row adders to the number of defective cells read out, and the results are written into the column and row address fail count memories. The number of defective cells is read out of the column address fail count memory and compared with a number of row spare lines of the memory under test. When the former is greater than the latter, the column address is decided as a failing address line, is counted by a failing address line counter and is written into a failing address memory. The row address is sequentially changed, beginning with a 0, at each failing column address when a "1" is read out of the failure analysis memory. The contents of the memories are each rewritten by subtracting a 1 therefrom and the fail counter is decremented by one.

REFERENCES:
patent: 3753244 (1973-08-01), Sumilas
patent: 4460997 (1984-07-01), Harns
patent: 4460999 (1984-07-01), Schmidt
patent: 4586178 (1986-04-01), Bosse
patent: 4635190 (1987-01-01), Meyer
patent: 4736373 (1988-04-01), Schmidt
patent: 4833652 (1989-05-01), Isobe
patent: 4837747 (1989-06-01), Dosaka
patent: 5091884 (1992-02-01), Kagami
M. Tarr, et al, "Defect Analysis System Speeds Test and Repair of Redundant Memories", Electronics International, vol. 57, pp. 175-179, Jan. 1984, New York.
IBM Technical Disclosure Bulletin, vol. 31, No. 12, May 1989, pp. 107-108.
IBM Technical Disclosure Bulletin, vol. 32, No. 3A, Aug. 1989, pp. 427-428.

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