Analytical model for predicting the operating process window...

Details Analytical model for predicting the operating process window... Analytical model for predicting the operating process window...

2001-03-30

2003-08-12

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06606738

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to methods of fabricating semiconductor devices, and more particularly, to a trim etch process that trims or reduces the critical dimension (CD) of the gate pattern in a resist mask.
2. Discussion of the Related Art
The trend toward ultra large-scale integration (ULSI) in semiconductor technology, directed toward an effort to build integrated circuits with more and faster semiconductor devices, has a result in continued shrinking of critical dimensions of the devices. For example, in circuits having field—effect transistors, a very important process step is the formation of the gate for each of the transistors, and in particular the width of the gate. In many applications, the switching speed and size of the transistor are functions of the width of the transistor gate. A narrower gate tends to produce a higher performance, i.e. a faster transistor which is also smaller in size, i.e., narrower in width.
The limitations of conventional lithographic techniques, which are used to pattern the gate during device fabrication, are quickly being realized Accordingly, there is a continuing need for more efficient and effective fabrication processes for forming transistor gates that are smaller and/or exhibit higher performance.
One technique for achieving narrower gate width is that of trim etch, undertaken on a resist line
10
on a substrate
12
(FIG.
1
), which resist line
10
is used to form the gate. Using conventional lithographic techniques, the resist line
10
has a width, called the Develop Inspect Critical Dimension (DICD), that is wider than the desired gate to be formed. For example, a typical deep-UV stepper in certain embodiments provides reliable resolution capabilities down to 0.25 microns. To provide for gate width that is less than 0.25 microns, the 0.25 micron wide resist line is isotropically etched in a controlled manner in a high-density plasma etching system, to provide etching in horizontal directions A
1
, A
2
along with etching in the vertical direction B, until a narrower final line, having a final critical dimension (FICD), remains.
Since a resist line with a relatively large DICD requires a relatively long trim etch time to achieve a given FICD, a significant amount of the resist is normally etched away in a vertical direction B, resulting in a substantial weakening and thinning of the photoresist
10
. This significant reduction of the vertical dimension or thickness of the photoresist
10
from its untrimmed vertical dimension can promote discontinuity thereof, resulting in the photoresist
10
being incapable of providing effective masking in the fabrication of the gate. In the case of a relatively small DICD, a resist with a small vertical resist dimension is required in order to prevent pattern collapse and/or bending caused by capillary actions during the lithography process, due to an undesirably high aspect ratio (AR), i.e., height/width ratio, of the partially etched resist structure.
A trim etch process is required to maintain a balance between vertical resist etch or erosion and horizontal resist trim. In an optimum process, given resist thickness and type, in order to minimize FICD, there is an optimum DICD which will enable the smallest FICD to be obtained. This is given by the intersection of the aspect ratio and erosion limits. However, for the same resist thickness and type, and DICD, if the ratio R
v
/R
h
(R
v
=vertical resist erosion rate, R
h
=horizontal resist trim rate=sum of trim rates in A
1
, A
2
directions) is lower than optimum, a feature trimmed with this process will fail earlier (i.e., at a larger FICD) than the optimum process, due to pattern collapse or bending. Furthermore, again for the same resist thickness and type, and DICD, if the ratio R
v
/R
h
is higher than optimum, a feature trimmed with this process will again fail earlier (i.e., at a larger FICD) than the optimum process, in this case due to excessive resist erosion, i.e., insufficient resist is left to mask the remainder of the polysilicon etch process.
Therefore, what is needed it is a method for modeling, predicting and defining a trim etch process so as to overcome the above problems.
SUMMARY OF THE INVENTION
The present invention is a method of trimming photoresist to form a mask for a layer of a semiconductor device, which layer may include polysilicon and/or nitride. The method is practiced substantially in accordance with:
w
min
=(
h
0
−R
v
t
max
)/
AR
max
where
w
min
=minimum width of trimmed photoresist;
h
0
=height of photoresist prior to trim;
R
v
=resist vertical etch rate;
t
max
=maximum etch time to reach resist vertical etch limit;
AR
max
=maximum allowable aspect ratio.
The present invention is further a method of trimming photoresist to form a mask for a layer of a semiconductor device, which layer may include polysilicon and/or nitride. The method is practiced substantially in accordance with:
w
0
=(
h
0
−R
v
t
max
)/
AR
max
+R
h
t
max
where
w
0
=width of photoresist prior to trim;
h
0
=height of photoresist prior to trim;
R
v
=resist vertical etch rate;
t
max
=maximum etch time to reach resist vertical etch limit;
AR
max
=maximum allowable aspect ratio;
R
h
=horizontal resist etch rate.


REFERENCES:
patent: 5256505 (1993-10-01), Chen et al.
patent: 5340700 (1994-08-01), Chen et al.
patent: 6121155 (2000-09-01), Yang et al.

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