Analysis techniques for multi-level memory

Details Analysis techniques for multi-level memory Analysis techniques for multi-level memory

2011-05-31

2011-05-31

Gaffin, Jeffrey A (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S720000, C714S721000, C714S723000, C365S201000

Reexamination Certificate

active

07954018

ABSTRACT:
A system and method for defect analysis of multi-level memory cell devices and embedded multi-level memory in system-on-chip integrated circuits are disclosed wherein a defect data set is input into the system. When a defect data set is received, an automated test engineering system running a memory test program analyzes the defect data set to generate one or more fail bit locations and one or more fail states of the memory. The multi-level memory defect analysis system and method then classify failed bits or patterns comprising a vertical fail pattern, whereby after being classified, each memory cell failure vertical fail pattern has three data attributes comprising fail type, a number of fail bits/states, and a sequence of the fail states. The vertical fail pattern may comprise a single fail state or multi-state fail. The multi-state fail may be a continuous-states fail, discontinuous-states fail, or all-state fail. The multi-level memory defect analysis system and method may additionally enable classification of failed bits or patterns comprising a lateral fail pattern. The lateral fail pattern may be a gradual fail pattern, periodic fail pattern, or random fail pattern.

REFERENCES:
patent: 6058495 (2000-05-01), Lee et al.
patent: 6470229 (2002-10-01), Wang et al.
patent: 6519725 (2003-02-01), Huisman et al.
patent: 6701477 (2004-03-01), Segal
patent: 6795942 (2004-09-01), Schwarz
patent: 6950771 (2005-09-01), Fan et al.
patent: 7075822 (2006-07-01), Elmhurst et al.
patent: 7370251 (2008-05-01), Nadeau-Dostie et al.
patent: 2003/0140276 (2003-07-01), Sagatelian
patent: 2007/0150777 (2007-06-01), Sasaki
patent: 2007/0255982 (2007-11-01), Adsitt
patent: 2008/0005630 (2008-01-01), Adsitt
Redeker, M., et al., “Fault Modeling and Pattern-Sensitivity Testing for a Multilevel DRAM”, IEEE 2002, 6 pgs.

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