Analysis of untestable faults using discrete node sets

Details Analysis of untestable faults using discrete node sets Analysis of untestable faults using discrete node sets

1994-06-10

1996-08-20

Nguyen, Hoa T.

39518313, 39518315, G01R 3128

Patent

active

055487157

ABSTRACT:
This invention teaches a system (10) and method for analyzing a fault within a model of a logic circuit. The method includes the computer executed steps of (a) building a fault model of the circuit model; (b) for each modelled fault that is determined to be untestable, (b) building a discrete node set comprised of nodes of the circuit model that are relevant to the untestable fault; and (c) outputting the discrete node set for analysis. The step of building a fault model includes a step of classifying the untestable faults into at least three categories including unobservable faults, excitation conflict faults, and reverse and forward implication (RFI) conflict faults. Faults from each of these three classifications are processed differently so as to build a relevant discrete node set for subsequent analysis.

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