Analysis method for semiconductor device, analysis system...

Details Analysis method for semiconductor device, analysis system... Analysis method for semiconductor device, analysis system...

2005-12-13

2005-12-13

Bui, Bryan (Department: 2863)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

C702S183000, C714S048000, C700S073000, C700S121000

Reexamination Certificate

active

06975953

ABSTRACT:
An analysis method for a semiconductor device includes measuring electrical characteristics of TEGs fabricated on a semiconductor substrate; classifying the TEGs into a first TEG category where a systematic failure has not occurred and a second TEG category where the systematic failure has occurred based on the electrical characteristics; creating a first comparison Mahalanobis reference space using first parameters of the TEGs in the first TEG category from among parameters of the TEGs expressed as numerical values; calculating a first comparison Mahalanobis distance of the first parameters and a second comparison Mahalanobis distance of second parameters of the TEGs in the second TEG category by using the first comparison Mahalanobis reference space; and comparing the first and second comparison Mahalanobis distances.

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Taguchi, “Mathematics for Quality Engineering,” Japanese Standards Association (1999), pp. 131-156.
Notice of Grounds for Rejection, issued by the Japanese Patent Office, mailed Jul. 5, 2005, in Japanese Application No. P2003-048090, and English-language translation thereof.

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