Analog unidirectional serial link architecture

Details Analog unidirectional serial link architecture Analog unidirectional serial link architecture

2006-01-31

2006-01-31

Corrielus, Jean B. (Department: 2637)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S156000

Reexamination Certificate

active

06993107

ABSTRACT:
A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver. The system comprises a phase locked loop (PLL) control circuit, a phase rotator circuit, a phase buffer circuit, and an equalization driver circuit. The phase rotator circuit is configured to acquire a clock phase from the phase locked loop control circuit and modulo shift the clock phase into a desired phase angle. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop, a multi-stage voltage controlled oscillator, a voltage comparator, a PLL control logic, a digital to analog counter and a low pass filter. The fine loop includes the oscillator, a frequency divider, a phase-frequency detector, a charge pump and a loop filter.

REFERENCES:
patent: 4918393 (1990-04-01), Yokosuka et al.
patent: 5276661 (1994-01-01), Beg
patent: 5422917 (1995-06-01), Scott
patent: 5539357 (1996-07-01), Rumreich
patent: 5621755 (1997-04-01), Bella et al.
patent: 5633895 (1997-05-01), Powell et al.
patent: 5719867 (1998-02-01), Borazjani
patent: 5799048 (1998-08-01), Farjad-Rad et al.
patent: 5812594 (1998-09-01), Rakib
patent: 5930231 (1999-07-01), Miller et al.
patent: 6002717 (1999-12-01), Gaudet
patent: 6144708 (2000-11-01), Maruyama
patent: 6347126 (2002-02-01), Nagayasu et al.
patent: 6466630 (2002-10-01), Jensen
patent: 6522702 (2003-02-01), Maruyama
patent: 6587521 (2003-07-01), Matui
patent: 6614840 (2003-09-01), Maruyama
patent: 6643787 (2003-11-01), Zerbe et al.
patent: 2004/0076192 (2004-04-01), Zerbe et al.
patent: 2004/0098634 (2004-05-01), Zerbe et al.
patent: 3707761 (1988-09-01), None
patent: 4411876 (1994-10-01), None
patent: 2000069102 (2000-03-01), None
Dossier CH919960004, “Receiving and Equalizing Signals for High-Speed Data Transmission”, pp. 1-7.
“Analog Integrated Circuits and Signal Processing”, Routama et al, vol. 19, No. 1, Apr., 1999, Kluwer Academic Publishers, pp. 59-74.
“Unilink 2.5 Gigabit SerDes Core” Product Brief, Routama et al, Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers, vol. 19, No. 1, Apr., 1999, p. 1.
“Building on our strength for success”, IBM InfiniBand Products, Feb. 15, 2001, pp. 1-2.
International Search Report dated Oct. 6, 2002 re Application No. PCT/GB 02/00143 filed Jan. 15, 2002.

Affiliated with

Also associated with

Rating

Analog unidirectional serial link architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Analog unidirectional serial link architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Analog unidirectional serial link architecture will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3578038