Analog-to-digital converter with successive approximation

Details Analog-to-digital converter with successive approximation Analog-to-digital converter with successive approximation

1999-04-19

2001-04-17

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000

Reexamination Certificate

active

06218976

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a process for analog-to-digital conversion and a device for analog-to-digital conversion (ADC), preferably a process for analog-to-digital conversion employing a successive approximation principle (SA-ADC).
STATE OF THE ART
In digital signal processing it is necessary to be able to convert an analog signal to a digital signal. There are different types of analog-to-digital converters, which substantially differ in cost and performance. The cost is determined by the circuit complexity of the analog-to-digital converter and the technology required to implement circuit components with said circuit complexity. The performance is typically measured in terms of conversion rate, resolution and power consumption.
An analog-to-digital converter (ADC) employing the successive approximation principle (SA-ADC) is controlled by an algorithm, such as binary search. The analog-to-digital converter comprises in principle a sampling unit storing a momentary value of an input signal, a digital-to-analog converter (DAC) generating known reference values and a comparator comparing the stored value to a reference value. The algorithm controls the sequence of reference values in such a manner that the stored value can be determined according to a measuring scale, normally an integer represented by binary numbers. This principle is limited by a causal requirement, where a comparison must have been finalized before the algorithm can find out which reference value is to be used in the next comparison. This cycle delimits the maximum rate of a SA-ADC.
Another problem is the accuracy of the reference values. In an electric circuit, a value is set according to an exponential curve, i.e., the longer time there is available, the more accurate becomes the value. This can result in dynamical errors and is a rate depending problem. Said problem can be solved by a redundant code, see M. P. V. Kolluri, “A 12-BIT 500-NS Subranging ADC”, IEEE Journal of Solid State Circuits, vol. 24, no. 6, pp. 1498-1506, December 1989; alternatively a plurality of comparators and a plurality of reference levels can be used, see P-E Danielsson, “A/D-conversion employing successive approximation with dual comparators”, Report No. LiTH-ISY-R-1796, 951004, Linköpings Universitet.
DISCLOSURE OF THE INVENTION
A problem with the conversion of an analog signal value to a digital signal value employing a successive approximation principle is that such a process, according to prior art, comprises a rate limiting factor depending on its approximation process.
An object of the present invention is to increase the rate of the approximation process by an improved division of a search interval and therein arranged reference levels.
The present invention solves the above mentioned problem by defining for each search interval at least three areas, so that said areas cover the entire search interval and so that each area covers at least one other area; that each such area is defined to a new smaller search interval until a last search interval reaches a pre-set value; that a reference value is defined within each redundant part, so that N areas in a search interval give N-1 reference values; that at least one reference level in each search interval is defined to coincide with at least one other reference level, where at least one such coinciding reference level belongs to two search intervals formed by areas in a nearest larger search interval.
In order to achieve said digital signal value, an unknown sampled value is compared to all reference levels in a search interval, whereby at least one area in said search interval can be eliminated, and at the proceeding successive approximation process, the unknown sampled value is compared to all reference value in the new smaller search interval, where each choice of comparative reference level is independent of the result in the nearest preceding step, until said unknown sampled value can be determined with a pre-set accuracy.
The above described process can advantageously be implemented in an analog-to-digital converter.
An advantage of the present invention is that the approximation process can be made with low requirements of convergence.
Another advantage of the present invention is that it only comprises one comparator.
Yet another advantage with the present invention is that it facilitates a high rate implementation.
The invention will now be further described by preferred embodiments and with reference to the accompanying drawings.


REFERENCES:
patent: 3646586 (1972-02-01), Kurz
patent: 0 406973 A1 (1991-01-01), None
patent: 2 148938 (1985-05-01), None
“A 12-Bit 500-NS Subranging ADC”, IEEE Journal of Solid State Circuits, vol. 24, No. 6, pp. 1498-1506, Dec. 1989.
“A/D-conversion employing successive approximation with dual comparators”, Report No. KiTH-ISY-R-1796, 951004, Linköpings Universitet.

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