Analog-to-digital converter

Details Analog-to-digital converter Analog-to-digital converter

2000-06-16

2002-04-23

Lam, Tuan T. (Department: 2816)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S158000

Reexamination Certificate

active

06377200

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 1999-22497, filed on Jun. 16, 1999, the contents of which are herein incorporated by reference in their entirety.
1. Field of the Invention
The present invention relates to an analog-to-digital converter, and more particularly to an analog-to-digital converter operable in a high speed operation.
2. Background of the Invention
An analog-to-digital converter (ADC), converting an analog signal to a digital signal, has many applications in electronic signal processing systems. In particular, the ADC is becoming a more useful component in accordance with an increase of mixed-mode systems. It may be proper for the advanced mixed-mode systems, DVDP (digital video disk player) or DBSR (direct broadcasting for satellite receiver), which would be the foremost applications in the market of household electrical appliances, to be manufactured with low cost and in a one-chip by a CMOS process. For the purpose of that, it is important to provide an ADC capable of conducting a radio frequency (RF) signal of high bandwidth to the system. Such an ADC may be on desire of being operable in high frequency over 100 MHz and having the characteristic of a medium resolution.
Now, among the ADCs of various types proposed by now, “flash” ADC has been disclosed in IEEE Journal of Solid State Circuit on December 1979 (Vol. SC-14, pp. 926~932) by Andrew G. F. Dingwall. In the Dingwall's flash ADC, an input signal is compared with reference voltages that are of different levels each other and converted into a digital signal at once, by means of amplifiers the number of which corresponds to a predetermined resolution. The flash ADC is advantageous for a fast conversion adaptable to an operating frequency of the one-chip mixed system even though it has a number of circuit elements. As shown in
FIG. 1
, the flash ADC is composed of reference voltage generator
10
, amplifying circuit
20
, and latch circuit
30
. The reference voltage generator
10
establishes 64 reference voltage levels Vref
1
~Vref
64
from two external reference voltages Vreft and Vrefb between which 65 resistors R
1
~R
65
are connected in serial. Pre-amplifiers PA
1
~PA
64
of the amplifying circuit
20
are differential amplifiers receiving the reference voltages Vref
1
~Vref
64
and input voltage Vin. Sixty-four latches L
1
~L
64
of the latch circuit
30
receives and stores amplified voltages VA
1
~VA
64
from the pre-amplifiers PA
1
~PA
64
. Each of output data bits DO
1
~DO
64
generated from the latch circuit
30
is set into six bits by a coding process.
Although the flash ADC of
FIG. 1
can accomplish a function of fast and precise data conversion, there are static offsets (most physical) at the pre-amplifiers due to a variation of manufacturing process, external noises, or element parameters. The static offsets would cause the amplifying precise to be worse and a reliable conversion to degrade thereby. In order to eliminate the static offsets, there has proposed of “auto-zero function” in which sampling operations for the difference between the reference voltages Vreft and Vrefb and for the offsets at the pre-amplifiers are employed. However, such auto-zero function does not overcome a limitation of an increase of RC delay time due to sampling capacitors and an operation speed of the amplifier itself, being impossible to accomplish a flash ADC operable in a very high frequency over 100 MHz.
Other techniques to promote the processing speed of the ADC have been proposed in various types. In “A 200 Msample/S 6 b flash ADC in CMOS” (ISSCC Dig. Tech. Papers, Febuary 1996, pp. 320~321), there is provided a specific period assigning to the auto-zero operation and inhibiting a normal operation of the ADC. Nevertheless, that is not available for a general application, just for very specific application.
In “A CMOS 6-b 200 Msample/s 3V supply converter for a PRML read channel LSI” (IEEE J. Solid State Circuit, Vol. 31, No. 11, pp. 1248~1257, September 1996), dummy amplifiers are additionally provided thereto and the static offsets of the amplifiers are removed by activating the dummy and existed amplifiers in alternative operating modes. It needs a complex circuit arrangement in constructing switches for alternatively selecting the amplifiers and circuits for performing timing operations against the switches.
The fast accessing with a high frequency analog signal is determined by bandwidths and slew rates of analog blocks, while the processing speed with a digital signal accords mostly to a latching time, meta-stability, and a propagation delay time. Although the highest frequency of an analog input signal available to be converted into a digital signal is a half of a clock frequency (according to a theoretical analysis), it is substantial to obtain the operating frequency of 10~20 MHz because of a weak current drivability with the analog circuit block even when the ADC operates in hundreds mega-Hertz. Such insufficient drivability occurs at the top and bottom amplifiers, e.g., PA
1
and PA
64
in
FIG. 1
, very seriously. Referring to FIGS.
2
A~
2
C, the top reference voltage Vref
1
as the lowest one is located too low, relative to the input voltage Vin. The small votage difference would cause instability of the amplifying operation due to short periods for high and low levels, PH and PL. Although the current drivability of the amplifiers PA
64
and PA
1
becomes larger therefrom to increase their amplifying ratios, it is hard to overcome the disharmony between the reference voltages. Since the increase amplifying ratios against the input voltage Vin also makes the swing-depth be larger, the amplifiers PA
64
and PA
1
can not generate their normal output voltages VA
64
and VA
1
of high and low levels when the input voltage Vin is higher than their corresponding reference voltages Vref
64
and Vref
1
, as shown in
FIGS. 2A and 2B
, respectively. The amplifiers PA
64
and PA
1
can do nothing but generating normal-low and high level output signals, VA
64
and VA
1
respectively. Furthermore, the larger swing depth due to the increased drivability causes timing discords between the input voltage Vin and the mostly one-sided output signals VA
64
and VA
1
, each of the output signals being incapable of following the oscillation of Vin. The two figures about VA
64
and VA
1
are extreme cases for the malfunction and timing discord. The nearer the top or bottom reference voltages is easier to cause the malfunctions with the output signals from the amplifiers. All those problems may act as a limitation of carrying out the fast conversion, restricting an allowable frequency that is desirable to be high in the ADC.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide an ADC capable of performing a faster conversion and a higher resolution.
In order to attain the above object, according to an aspect of the present invention, there is provided an analog-to-digital converter including: a reference generator circuit for generating a plurality of reference voltages; a plurality of amplifying comparators for recieving the reference voltages and analog input signals, each amplifing comparator including: two amplifying paths, each of which has a first amplifier and a second amplifier for alternatively receiving signals from the two paths; a latching comparator having a plurality of latches and receiving output signals from the amplifying comparator; and a digital decoder receiving output signals from the latching comparator and generating a predetermined number of data bits.
Amplifying periods through the two paths are overlapped for predetermined time each other. The amplifying comparator further includes a capacitor for sampling an offset voltage of the first amplifier; a first switch for shorting input and output terminals of the first amplifier; a second switch for resetting the output signals from the first amplifier into a predetermined voltage level in response to a clock signal; and a plurality of switches for controlling a transfer

Affiliated with

Also associated with

Rating

Analog-to-digital converter does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Analog-to-digital converter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Analog-to-digital converter will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2827731