Analog PLL clock recovery circuit and a LAN transceiver employin

Details Analog PLL clock recovery circuit and a LAN transceiver employin Analog PLL clock recovery circuit and a LAN transceiver employin

1993-07-06

1995-09-05

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375373, 331 17, 327156, 327299, H04L 700, H04L 2536, H04L 2540, H03D 324

Patent

active

054485983

ABSTRACT:
A VSLI transceiver chip incorporating an improved analog PLL circuit for recovering a digital clock signal from a digital data signal having pulse widths which may vary during each data cycle. The analog PLL clock recovery circuit comprises a phase detector, a gain control circuit, a variable current charge pump, a loop filter and a variable frequency oscillator. The phase detection means for detecting, during each data cycle, the phase error between the digital data signal and recovered digital clock signal, and produces first end second digital control pulse signals in response to the detection of the phase error. The gain control means produces third and fourth digital control pulse signals during each data cycle. The value of the third and fourth control pulse signals during each data cycle depends on the value of the digital data signal, the value of the recovered clock signal, and the value of the second digital control pulse signal during the data cycle, and the change in value of the third and fourth control pulse signals is responsive to the change in the value of the recovered digital clock signal. The variable current charge pump receives the first and second digital control pulse signals. The recovered digital clock signal is produced by variable frequency oscillator, having a clock frequency proportional to the produced analog control signal.

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Devito, et al., "A 52 Mhz and 155 MHz Clock-Recovery PLL", Analog Devices Semiconductor Division, Wilmington, Mass., DIGEST OF TECHNICAL PAPERS, IEEE International Solid-State Ciruits Conference, 1991.
Lee, et al. "A 155 MHz Clock Recovery Delay and Phase-Locked Loop", Analog Devices Semiconductor Division, Wilmington, Mass., DIGEST OF TECHNICAL PAPERS, IEEE International Solid-State Ciruits Conference, 1992.

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