Analog MOS semiconductor device, manufacturing method...

Details Analog MOS semiconductor device, manufacturing method... Analog MOS semiconductor device, manufacturing method...

2002-03-27

2004-05-04

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06732334

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an analog MOS semiconductor device, such as an operational amplifier, a comparator, an analog switch, a sense amplifier for a memory, a low noise amplifier, or a mixer, including a MOS transistor, a capacitor, a resistor, an inductor, a diode, etc., and also relates to a method for manufacturing the same.
In recent years, along with the development in the system on chip technology, more and more LSIs including analog circuits and digital circuits integrated together have been developed each year. Accordingly, there is a demand for a significant reduction in the development time and the number of development steps and for improving the performance. There is also a demand for an automated layout process for an analog MOS semiconductor circuit.
A conventional analog MOS semiconductor device will now be described.
FIG. 23
illustrates a circuit configuration of an operational amplifier as an analog MOS semiconductor device. The operational amplifier illustrated in the figure includes a P-channel transistor MP
1
(
21
), a P-channel transistor MP
2
(
22
), a P-channel transistor MP
5
(
25
), a P-channel transistor MP
6
(
26
), an N-channel transistor MN
3
(
23
), an N-channel transistor MN
4
(
24
), an N-channel transistor MN
7
(
27
), a capacitor Cc (
28
), and a resistor Rc (
29
). The operational amplifier also includes a positive side input terminal V+ (
30
), a negative side input terminal V− (
31
), an output terminal Vo (
32
), a bias voltage input terminal VBIAS (
33
), a positive side power supply VDD (
34
), and a negative side power supply VSS (
35
).
Table 1 below shows the channel width W and the channel length L of each of the MOS transistors MP
1
to MN
7
, the resistance value of the resistor Rc, and the capacitance value of the capacitor Cc of the operational amplifier of
FIG. 23
, as an example of the results of a design process.
TABLE 1
W (&mgr;m)
L (&mgr;m)
MP1
121.20
1.00
MP2
121.20
1.00
MN3
28.00
0.50
MN4
28.00
0.50
MP5
56.00
0.50
MP6
406.00
0.50
MN7
406.00
0.50
Rc
6.84 k&OHgr;
Cc
3.62 pF
FIG. 24
illustrates a conventional layout of the operational amplifier of FIG.
23
. The size of each of the seven transistors MP
1
(
21
) to MN
7
(
27
) in
FIG. 24
represents a layout area occupied by the transistor according to the channel width W and the channel length L thereof. This similarly applies to the capacitor Cc and the resistor Rc.
A condition for realizing systematic offset voltage SVoff=0 in a circuit design of an operational amplifier is shown by Expression (4.182) on page 210 in “Analog MOS Integrated Circuit For Signal Processing”, R. Gregorian, G. C. Temes, John Wiley & Sons. Applying this expression to the operational amplifier of
FIG. 23
, the following expression needs to hold:
(W/L)MN
3
/(W/L)MN
7
=(
W/L
)
MN
4
/(
W/L
)
MN
7
=(
W/L
)
MP
5
/(
W/L
)
MP
6
/2  (1)
The channel width W and the channel length L of the transistors are determined so as to satisfy Conditional Expression (1) above.
Furthermore, a condition for realizing random offset voltage RVoff=0 in a circuit design of an operational amplifier is shown by Expression (4.185) on page 211 in the same article. Applying the expression to the operational amplifier of
FIG. 23
, the following expression needs to hold:
(
W/L
)
MP
1
=(
W/L
)
MP
2
  (2)
In the operational amplifier configuration, the P-channel transistor MP
1
(
21
) and the P-channel transistor MP
2
(
22
) are a pair of transistors that together form a differential input circuit.
Similarly, another condition for realizing random offset voltage RVoff=0 is shown by Expression (4.183) on page 211 in the same article. Applying the expression to the operational amplifier of
FIG. 23
, while taking into consideration the preconditions for the expression set forth in this article, the following expression needs to hold:
(
W/L
)
MN
3
=(
W/L
)
MN
4
  (3)
In the operational amplifier configuration, the N-channel transistor MN
3
(
23
) and the N-channel transistor MN
4
(
24
) are a pair of transistors that together form a current mirror. The value of the capacitor Cc and the value of the resistor Rc are determined so that the phase margin of the operational amplifier is satisfied as described in the article.
However, even if the channel width W and the channel length L of the seven transistors MP
1
(
21
) to MN
7
(
27
) are designed so as to satisfy Conditional Expression (1) for realizing systematic offset voltage SVoff=0 as described above, the value of the channel width W of each transistor may be slightly shifted from the design value due to various process errors occurring in a semiconductor manufacturing process. As a result, seven transistors that are actually obtained as described above do not satisfy Conditional Expression (1) for realizing systematic offset voltage SVoff=0, whereby a systematic offset voltage SVoff occurs. A systematic uniform shift will now be described. This shift is shown in
FIG. 25
with the P-channel transistor MP
5
(
25
) as an example.
FIG. 25
shows, on the left side, an example of a layout of the P-channel transistor MP
5
(
25
) using the design values described above. The transistor includes a gate
7
in the central position, and a source
6
and a drain
8
arranged on the opposite sides of the gate
7
. The source
6
and the drain
8
are connected to aluminum wires
9
and
9
via contacts
10
. Moreover, a P-type impurity diffusion region
11
is provided for forming a channel of a P-channel transistor, and the channel width W of the P-channel transistor MP
5
(
25
) that is drawn on the left side of the figure is designed to be equal to the width of the P-type impurity diffusion region
11
.
As an example, it is assumed that a uniform process error of &Dgr;W occurs in the decreasing direction in the semiconductor manufacturing process.
FIG. 25
shows, on the right side, the manufactured P-channel transistor MP
5
(
25
). The width of the P-type impurity diffusion region
11
of the P-channel transistor MP
5
(
25
) that is drawn on the right side of the figure is reduced by &Dgr;W at each end, and thus the width is reduced by 2&Dgr;W in total. Therefore, the actual channel width W of the manufactured P-channel transistor MP
5
(
25
) is expressed as follows:
(W−2&Dgr;W)MP
5
  (4)
Similarly, the process error in the semiconductor manufacturing process occurs uniformly for other transistors of the operational amplifier illustrated in FIG.
23
. Therefore, the actual channel widths W of the manufactured transistors are expressed as follows:
(W−2&Dgr;W)MN
3
  (5)
(W−2&Dgr;W)MN
4
  (6)
(W−2&Dgr;W)MP
6
  (7)
(W−2&Dgr;W)MN
7
  (8)
Therefore, substituting Expressions (3) to (8) into Expression (1) gives the following expression:
{(W−2&Dgr;W)/L}MN
3
/{(W−2&Dgr;W)/L}MN
7
={(
W−
2
&Dgr;W
)/
L}MN
4
/{(
W−
2
&Dgr;W
)/
L}MN
7
≠{(
W−
2
&Dgr;W
)/
L}MP
5
/{(
W−
2
&Dgr;W
)/
L}MP
6
/2  (9)
Thus, the conditional expression for realizing systematic offset voltage SVoff=0 no longer holds. Therefore, the systematic offset voltage SVoff occurs due to various systematic process errors in the semiconductor manufacturing process.
On the other hand, the article, page 211, line 15 from the bottom to line 12 from the bottom, states that in the circuit configuration of an analog MOS semiconductor device, Conditional Expression (1) for realizing systematic offset voltage SVoff=0 can be satisfied as follows: “If ratios as large as (or larger than) two are required, then the wider transistor can be realized by the parallel connection of two (or more) “unit transistors” of the size of the narrower one”. Specifically, with a transistor (first transistor) having the minimum channel width W being a unit transistor, when a second transistor having a

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