An EEPROM Circuit, a memory device having the EEPROM circuit and

Static information storage and retrieval – Read/write circuit

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36518903, G11C 1300

Patent

active

054306752

ABSTRACT:
In an EEPROM, source electrodes S of memory cell transistors MT1 to MTn are grounded, via transistors MG1 to MGn. The source electrodes S are separated from each other so as to maintain the source electrode S of each of the memory cell transistors MT1 to MTn at an open state, even when a leak path is formed by the memory cell transistor MTi in the written state (low threshold voltage). In the EEPROM, an EPROM circuit in which the write operation can be continuously performed without the erase operation can be obtained. Further, an EEPROM circuit having the nonerasable region (the region which functions as the EPROM) and the erasable region (the region which functions as the EEPROM) can be also provided.

REFERENCES:
patent: 4752911 (1988-06-01), Prevost et al.

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