Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2005-10-18
2005-10-18
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S205000, C365S189090, C365S189110, C365S185210
Reexamination Certificate
active
06956781
ABSTRACT:
When a first memory cell storing data ‘0’ is read, an associated word line is set at an ‘H’ level, and an associated NMOS is turn on by a signal having an ‘H’ level so as to select the first memory cell. In the first memory cell, a drain voltage is reduced to a grounding level via the NMOS, and an electrical potential difference is generated between a source and the drain. However, no channel is formed so that no electrical current flows. Since a parasitic capacitance exists between associated bit lines, the electrical potential of a node is reduced to the ground level due to the coupling effect of the parasitic capacitance. Accordingly, a charging current flows to the node. In addition, a direct current flows from the node to the ground via another NMOS. Consequently, electrical charging to the parasitic capacitance starts earlier, and a reading delay time can be reduced.
REFERENCES:
patent: 5877985 (1999-03-01), Banba et al.
patent: 5917765 (1999-06-01), Morishita et al.
patent: 6072742 (2000-06-01), Ooishi
patent: 6411549 (2002-06-01), Pathak et al.
patent: 2000-331486 (2000-11-01), None
Elms Richard
Nguyen Tuan T.
Oki Electric Industry Co. Ltd.
Volentine Francos & Whitt PLLC
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