Amorphous silicon interconnect with multiple silicon layers

Details Amorphous silicon interconnect with multiple silicon layers Amorphous silicon interconnect with multiple silicon layers

1999-03-01

2000-12-26

Hardy, David

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Amorphous semiconductor material

257 60, 257 61, 257 55, 257758, H01L 2904, H01L 31036, H01L 310376, H01L 3120, H01L 2348

Patent

active

061663956

ABSTRACT:
In one aspect, the invention includes a semiconductor processing method comprising depositing a silicon layer over a substrate at different deposition temperatures which at least include increasing the deposition temperature through a range of from about 550.degree. C. to about 560.degree. C. In another aspect, the invention includes a semiconductor processing method comprising, in an uninterrupted deposition process, depositing a silicon layer which comprises an essentially amorphous silicon region, an essentially polycrystalline silicon region, and a transition region interconnecting the essentially amorphous silicon region and the essentially polycrystalline silicon region, the essentially amorphous silicon region having an amorphous silicon content which is greater than or equal to about 90 weight percent of a total material of the amorphous silicon region, the essentially polycrystalline silicon region having a polycrystalline silicon content which is greater than or equal to about 90 weight percent of a total material of the polycrystalline silicon region, the transition comprising an amorphous silicon content and a polycrystalline silicon content, the transition region being defined as a region having both a lower amorphous silicon content than the essentially amorphous silicon region and a lower polycrystalline silicon content than the essentially polycrystalline silicon region, the transition region being at least 45 Angstroms thick.

REFERENCES:
patent: 4829024 (1989-05-01), Klein et al.
patent: 4833519 (1989-05-01), Kawano et al.
patent: 5583070 (1996-12-01), Liao et al.
patent: 5597754 (1997-01-01), Lou et al.
patent: 5618747 (1997-04-01), Lou
patent: 5691228 (1997-11-01), Ping et al.
patent: 5691249 (1997-11-01), Watanabe et al.
patent: 5714795 (1998-02-01), Ohmi et al.
patent: 5763306 (1998-06-01), Tsai
patent: 5801087 (1998-09-01), Manning et al.
patent: 5801427 (1998-09-01), Shiratake et al.
patent: 5825068 (1998-10-01), Yang
patent: 5840605 (1998-11-01), Tuan
patent: 5856007 (1999-01-01), Sharan et al.
patent: 5869389 (1999-02-01), Ping et al.
patent: 5874333 (1999-02-01), Chang et al.
patent: 5893747 (1999-04-01), Yang
patent: 5913125 (1999-06-01), Brouillette et al.
patent: 6015743 (2000-01-01), Zahurak et al.

Affiliated with

Also associated with

Rating

Amorphous silicon interconnect with multiple silicon layers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Amorphous silicon interconnect with multiple silicon layers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Amorphous silicon interconnect with multiple silicon layers will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-997747