Amorphous barrier layer in a ferroelectric memory cell

Details Amorphous barrier layer in a ferroelectric memory cell Amorphous barrier layer in a ferroelectric memory cell

1999-03-05

2001-02-27

Wilczewski, Mary (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S751000, C438S003000, C438S240000

Reexamination Certificate

active

06194754

ABSTRACT:

FIELD OF THE INVENTION
The invention generally relates to ferroelectric structures integrated onto substrates such as silicon. In particular, the invention relates to the fabrication process of producing a ferroelectric structure on a silicon or polysilicon surface.
BACKGROUND ART
Considerable interest exists in fabricating integrated circuit (IC) memories which are non-volatile, that is, ones that continue to store data after the IC chip has been powered down. One type that is reaching the market is a ferroelectric memory, in particular, a ferroelectric random access memory (FRAM). In an FRAM, the gap between the electrodes of a capacitor is filled with a spontaneously polarizable ferroelectric material which can be electrically poled into either of two stable states. The commercial activity to date has involved polycrystalline ferroelectric materials in ferroelectric cells integrated with silicon circuitry. Examples of the ferroelectric materials include lead zirconium titanate (PZT), lead lanthanum zirconium titanate (PLZT), lead niobium zirconium titanate (PNZT). Despite intensive developmental efforts, these polycrystalline ferroelectric IC memories suffer from low yield in manufacture mostly due to the absence of a good barrier layer between the oxygen-rich ferroelectric material and the oxygen-sensitive silicon.
In an alternative approach under development, the ferroelectric material is grown in a crystallographically oriented phase. It is believed that under the proper conditions the ferroelectric grows in a columnar multicrystalline structure with the <001> axis of the layered perovskite crystal structure of typical ferroelectrics being preferentially oriented normal to the ferroelectric film. Thereby, c-axis oriented columnar crystallites are formed with random orientation within the plane of the film.
In U.S. Pat. No. 5,777,356, incorporated herein by reference in its entirety, Dhote and Ramesh have disclosed an advantageous ferroelectric cell incorporating an intermetallic barrier layer. Aggarwal, Dhote and Ramesh have disclosed an improved annealing process for fabricating this structure in U.S. patent application, Ser. No. 08/871,057, filed Jun. 9, 1997. A structure envisioned in these two patent applications is illustrated in the cross-sectional view of FIG.
1
. An illustrated ferroelectric random access memory (FRAM) cell 20, of which many are formed in the IC memory, is formed on a <001>-oriented crystalline silicon substrate
22
and includes both a ferroelectric capacitor and a transistor. A metal-oxide-semiconductor (MOS) transistor is created by forming source and drain wells
24
,
26
having a conductivity type opposite to that of the substrate
22
. The intervening gate region is overlaid with a gate structure
28
including a lower gate oxide and an upper metal gate line, for example of aluminum, to control the gate.
A first inter-level dielectric layer
30
is deposited over the substrate and the transistor structure. A through hole
32
is etched through the first inter-level dielectric layer
30
in the area over the source well
24
, and polysilicon is filled into the through hole
32
to form a polysilicon contact plug to the transistor source. A metal source line
34
is photolithographically delineated on top of the first inter-level dielectric layer
30
and electrically contacts the polysilicon plug
32
.
A second inter-level dielectric layer
36
is then deposited over the first inter-level dielectric layer
30
. Another through hole
38
is etched through both the first and second inter-level dielectric layers
30
,
36
over the area of the drain well
26
, and polysilicon is filled into the second through hole
38
to form a contact plug to the transistor drain
26
.
A lower ferroelectric stack is then deposited and defined over the polysilicon plug
38
. It includes a polysilicon layer
40
to promote electrical contact to the polysilicon plug
38
, a titanium nitride (TiN) layer
42
acting as a first conductive barrier between the underlying polysilicon and the oxidizing ferroelectric layer and its oxide electrodes, an intermetallic layer
44
acting as the primary barrier, and a lower metal-oxide electrode
46
. The TiN layer
42
has been found to not be essential.
Growth of the metal-oxide electrodes
46
,
52
and the ferroelectric layer
50
is performed at temperatures in the range of 500° to 650° C., the highest temperatures achieved in the processing after the deposition of the intermetallic layer
44
.
The intermetallic layer
44
is novel to the cited earlier patent. It may have a composition of Ti
3
Al, among other possibilities to be discussed later. In brief, an intermetallic is an alloy of at least two metals, one of which is refractory, and the metals are conventionally combined in stoichiometric or near stoichiometric ratios. Conventionally, it has been understood that there results a metal with long-range atomic order, that is, a metal that is at least polycrystalline. Liu et al. provide a good introduction to intermetallics, at least the intermetallics having long-range order as used for mechanical components, in “Ordered Intermetallics,”
ASM Handbook, vol.
2
, Properties and Selection: Nonferrous Alloys and Special-Purpose Materials
(ASM International, 1992) pp. 913-942. The intermetallic layer
44
acts as an electrically conductive barrier to prevent the oxygen needed to fabricate the perovskite layers
46
,
50
,
52
from migrating downwardly while the perovskite are being deposited in an oxygen-rich environment at the relatively high temperatures of 500 to 650° C.
The lower metal-oxide electrode may have a composition of lanthanum strontium cobaltite (LSCO), and in particular a composition of approximately La
1−x
Sr
x
CoO
3
, where 0.15≧x≧0.85. A composition of x=0.5 is used in the examples. It is now well known that LSCO forms an acceptable electrical contact and further under the proper processing conditions promotes highly oriented growth of perovskite ferroelectric materials grown over it. That is, it acts as a templating layer. Alternative conductive metal oxides include among others strontium ruthenate (SrRuO
3
) and strontium vanadate (SrVO
3
). Several variations on the structure of the lower ferroelectric stack are possible. Neither the polysilicon layer
40
nor the TiN layer
42
is considered crucial, and either or both may be dispensed with.
A Z-shaped field-oxide layer
48
is formed around the sides of the lower ferroelectric stack and extends over its rim and laterally outwards from its bottom but leaves a central aperture for the after deposited upper ferroelectric stack.
The upper ferroelectric stack is then deposited and defined to fill the aperture of the field oxide layer
48
but not to extend beyond the end of its foot. The upper ferroelectric stack includes the ferroelectric layer
50
, for example of PNZT, the upper metal-oxide electrode layer
52
, for example of LSCO, and a platinum layer
54
.
A third inter-layer dielectric layer
56
is deposited around the upper and lower ferroelectric stacks. A via hole
60
is etched down to the platinum layer
54
, and Ti/W is filled into the hole to form a via
60
contacting the platinum layer
54
. An aluminum layer is deposited and delineated to form an interconnect line
62
connected to the via
60
.
Variations on this structure include replacement of the polysilicon with tungsten (W) or with a layered structure of TiN/W or of polysilicon/TiN/W.
Prototype ferroelectric capacitor stacks have been grown following the vertical stack structure shown in FIG.
1
. Both the LSCO electrodes
46
,
52
and the ferroelectric layer
50
have been shown to exhibit highly crystalline <00l> orientation when grown under the proper conditions. The ferroelectric stacks have been measured to have polarization, fatigue, and retention properties superior to those available from polycrystalline ferroelectric cells.
A very important characteristic of ferroelectric cells, if they are to be commercialized, is their aging or

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