Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-11-03
2001-07-03
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06256768
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of Invention
Invention relates to integrated circuit design, particularly to hierarchical layout display system and methodology for amoeba-type component perimeter placement.
2. Description of Background Art
Electronic circuit and system designs are becoming increasingly complex, sometimes having over ten million transistors. To handle such complex magnitude, circuit designs may be represented hierarchically. Furthermore, computer-aided design (CAD) tools facilitate definition and verification of logic-level, as well as physical-level design representations. Additionally, floor-planning and placement steps serve to convert design representation from logical to physical.
Floor-planning usually provides “high-level” block (i.e., rectangular) diagram representing hierarchical logic design, wherein such blocks may represent top or child-level components in design hierarchy. Moreover, automated placement tools may use floor-planning to provide “strict” or “loose” suggestion of preferred preliminary placement of sub-logic components within blocks. With strict floor-planning approach, components in each floor-plan block are generally placed in confines bordering correspondingly drawn block, whereas in loose floor-planning approach, automated placement algorithm generally has more freedom for components to lie beyond boundaries drawn in given hierarchy.
Oftentimes, however, design trade-offs arise, for instance, whereupon strictly enforced floor-planning results in undesirable longer wire connection lengths, which translate to physically larger and/or un-route-able layouts as compared to more loosely governed floor-plans. Hence, more strictly enforced floor-planning approach generally require unduly tedious effort to achieve desired physical design. But, such strictly enforced floor-planning may nonetheless offer designers better control, for example, over design timing, as well as more independent implementation of hierarchical sub-components. Furthermore, in comparison to such strict approach, relatively loose floor-planning, as well as so-called “flat” (i.e., non-hierarchical) automatic placement approaches tend to place components in generally non-hierarchy manner and shape, whereby resulting constraints may generate more route-able placements.
In view of various design tradeoffs, therefore, there is increased need to provide improved automated methodology and system to assist electronic design engineers to accomplish higher quality hierarchical circuit and system designs without unreasonable burden, particularly in terms of time, effort, and difficulty of use.
SUMMARY OF THE INVENTION
Invention resides in computer-implemented electronic design automation (EDA) software and associated processing firmware or hardware for circuit and/or system definition or verification, wherein designer visual feedback about hierarchical physical design is displayed in uniquely simplified and more intuitive manner. In particular, design floor-plan having “amoeba”-like generally less-structured cellular perimeter characteristics associated with hierarchical component groupings, sub-groupings, or super-groupings are generated by automated placement scheme.
Preferred placement process produces faster, more compact, and more easily analyzable physical design solution by determining perimeters of hierarchical circuit components or specified groupings thereof, according to unique amoeba-style algorithm associated with displaying actual observable perimeters for hierarchical circuit components.
In particular, present process achieves improved tool performance, in significant part, by computing perimeter values at each hierarchy level, then displaying amoeba-like closed rectilinear polygons formed by such perimeters. Physical design display of largely component perimeters is faster to draw than including lower-level component circuit details, as well as being visually less cluttered, and therefore intuitively easier for designers to understand at relatively higher level of circuit functionality.
Optionally, simplified display data including actual object perimeter information may be transmitted more efficiently over electronic network to share hierarchical design prototype as email or fax, for example, sent to other remote designer workstations for further analysis and verification thereof.
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Garbowski Leigh Marie
Silicon Perspective Corporation
Smith Matthew
Smith-Hill and Bedell
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