Ambiguous virtual channels

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C710S036000, C710S306000

Reexamination Certificate

active

07114043

ABSTRACT:
An apparatus comprises a first plurality of buffers configured to store operations belonging to a first virtual channel and a control circuit coupled to the first plurality of buffers. The first virtual channel includes first operations and second operations, wherein each of the first operations depend on at least one of the second operations during use. A first number of the first operations is less than or equal to a maximum. It is ambiguous, for a first received operation in the first virtual channel, whether the first received operation is one of the first operations or the second operations. A total number of the first plurality of buffers exceeds the maximum.

REFERENCES:
patent: 4433378 (1984-02-01), Leger
patent: 4463424 (1984-07-01), Mattson et al.
patent: 4760571 (1988-07-01), Schwarz
patent: 5640399 (1997-06-01), Rostoker et al.
patent: 5668809 (1997-09-01), Rostoker et al.
patent: 5778414 (1998-07-01), Winter et al.
patent: 5802287 (1998-09-01), Rostoker et al.
patent: 5829025 (1998-10-01), Mittal
patent: 5887187 (1999-03-01), Rostoker et al.
patent: 5893150 (1999-04-01), Hagersten et al.
patent: 5908468 (1999-06-01), Hartmann
patent: 5914955 (1999-06-01), Rostoker et al.
patent: 5974508 (1999-10-01), Maheshwari
patent: 6018763 (2000-01-01), Hughes et al.
patent: 6021451 (2000-02-01), Bell et al.
patent: 6092137 (2000-07-01), Huang et al.
patent: 6098064 (2000-08-01), Pirolli et al.
patent: 6111859 (2000-08-01), Godfrey et al.
patent: 6151662 (2000-11-01), Christie et al.
patent: 6157623 (2000-12-01), Kerstein
patent: 6202125 (2001-03-01), Patterson et al.
patent: 6202129 (2001-03-01), Palanca et al.
patent: 6209020 (2001-03-01), Angle et al.
patent: 6215497 (2001-04-01), Leung
patent: 6262594 (2001-07-01), Cheung et al.
patent: 6266797 (2001-07-01), Godfrey et al.
patent: 6269427 (2001-07-01), Kuttanna et al.
patent: 6279087 (2001-08-01), Melo et al.
patent: 6321309 (2001-11-01), Bell et al.
patent: 6332179 (2001-12-01), Okpisz et al.
patent: 6349365 (2002-02-01), McBride
patent: 6366583 (2002-04-01), Rowett et al.
patent: 6373846 (2002-04-01), Daniel et al.
patent: 6438651 (2002-08-01), Slane
patent: 6574708 (2003-06-01), Hayter et al.
patent: 2004/0066758 (2004-04-01), Van Doren et al.
patent: 2004/0068616 (2004-04-01), Tierney et al.
patent: WO 00/30322 (2000-05-01), None
patent: WO 00/52879 (2000-09-01), None
Linder, et al., “An Adaptive and Fault Tolerant Wormhole Routing Strategy for k-ary n-cubes”, © 1991 IEEE, p. 2-12.
Dally et al., “Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels”, © IEEE, p. 466-475.
Duato, “A Theory of Deadlock-Free Adaptive Multicast Routing in Wormhole Networks”, © 1995 IEEE, p. 976-987.
U.S. Appl. No. 09/680,524; filed Oct. 6, 2000; Rowlands et al.; “Source Triggered Transaction Blocking”.
U.S. Appl. No. 09/829,514; filed Apr. 9, 2001; Kruckemyer et al.; “Cache Coherent Protocol In Which Exclusive . . . ”.
U.S. Appl. No. 10/413,917; filed Apr. 15, 2003; Rowlands et al.; “Cache Programmable To Partition Ways To Agents . . . ”.
U.S. Appl. No. 10/269,922; filed Oct. 11, 2002; Sano et al.; “Systems Using Mix of Packet, Coherent,and Noncoherent . . . ”.
U.S. Appl. No. 10/270,028; filed Oct. 11, 2002; Rowlands; “System Having Interfaces, Switch, And Memory Bridge . . . ”.
U.S. Appl. No. 10/269,827; filed Oct. 11, 2002; Rowlands et al.; “Remote Line Directory Which Covers Subset of . . . ”.
U.S. Appl. No. 10/269,828; filed Oct. 11, 2002; Rowlands; “L2 Cache Maintaining Local Ownership Of . . . ”.
U.S. Appl. No. 10/270,480; filed Oct. 11, 2002; Rowlands; “System Having Address-Based Intranode Coherency and . . . ”.
SiByte; “Target Applications” http://sibyte.com/mercurian.applications.htm; Jan. 15, 2001; 2 pages.
SiByte; “SiByte Technology” http://sibyte.com/mercurian/technology.htm; Jan. 15, 2001; 3 pages.
SiByte; “The Mercurian Processor” http://sibyte.com/mercurian; Jan. 15, 2001; 2 pages.
SiByte; “Fact Sheet, SB-1 CPU” Oct. 2000; 1 page.
SiByte; “Fact Sheet, SB-1250” Oct. 2000; 10 pages.
Stepanian; “SiByte SB-1 MIPS64 CPU Core” Embedded Processo Forum 2000; Jun. 13, 2000, 15 pages.
Keller; “The Mercurian Processor: A High Performance, Power-efficient CMP for Networking” Oct. 10, 2000; 22 pages.
Saulsbury et al.; “An Argument for Simple COMA” SICS Research Report No.: R94:15; Aug. 1, 1994; 20 pages.
Lenoski; “The Design And Analysis Of Dash: A Scalable Directory-Based Multiprocessor” Dissertation-Stanford University; Dec. 1991; 176 pages.
“21143 PCI/Card Bus 10/100Mb/s Ethernet LAN Controller” Hardware Reference Manual; Intel Corp.; Oct. 1998.
“Pentium Pro Family Developer's Manual, vol. 1: Specifications” Intel Corporation; 1996; pp. 4-1 to 4-18.
“PowerPC 601, RISC Microprocessor User's Manual” MPC601UM/AD; 1993; 1 page.
“Pentium Processor Family User's Manual, vol. 1: Pentium Processor Family Data Book”; Intel Corp.; 1994; 2 pages.
Katevenis et al.; “ATLAS I: a single-chip, gigabit ATM switch with HIC/HS links and multi-lane back-pressure” Microprocessors and Microsystems; 1998; pp. 481-490.
Halfhill; “SiByte Reveals 64-Bit Core For NPUs, Independent MIPS64 Design Combines Low Power, High Performance” Microdesign Resources; Jun. 2000, 4 pages.
U.S. Appl. No. 09/680,524;filed Oct. 6, 2000; Rowlands et al.; “Source Triggered Transaction Blocking.”
U.S. Appl. No. 09/829, 514; filed Apr. 9, 2001; Kruckemyer et al.; “Cache Coherent Protocol In Which Exclusive...”
U.S. Appl. No. 10/413,917; filed Apr. 15, 2003; Rowlands et al.; “Cache Programmable To Partition Ways To Agents...”
U.S. Appl. No. 10/269,922; filed Oct. 11, 2002; Sano et al.; “Systems Using Mix of Packet, Coherent, and NonCoherent...”
U.S. Appl. No. 10/270,028; filed Oct. 11, 2002; Rowlands; “System Having Interfaces, Switch, And Memory Bridge...”
U.S. Appl. No. 10/269,827; filed Oct. 11, 2002; Rowlands et al; “Remote Line Directory Which Covers Subset of...”
U.S. Appl. No. 10/269,828; filed Oct 11, 2002; Rowlands; “L2 Cache Maintaining Local Ownership Of...”
U.S. Appl. No. 10/270,480; filed Oct. 11, 2002; Rowlands; “System Having Address-Based Intranode Coherency and...”

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Ambiguous virtual channels does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Ambiguous virtual channels, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ambiguous virtual channels will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3533307

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.