ALU implementation in single PLD logic cell

Details ALU implementation in single PLD logic cell ALU implementation in single PLD logic cell

2002-02-01

2002-11-05

Chang, Daniel D. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000, C708S232000, C708S235000

Reexamination Certificate

active

06476634

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to Programmable Logic Devices (PLDs). More particularly, the invention relates to an ALU (Arithmetic Logic Unit) implementation for a PLD that consumes only one PLD logic cell per bit of the ALU.
BACKGROUND OF THE INVENTION
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, RAM, and so forth).
The CLBs, IOBs, interconnect, and other logic blocks are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect are configured. The configuration data may be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Other types of PLDs are programmed using static memory, i.e., memory elements that are programmed once and retain that programming until erased or reprogrammed. These PLDs include, for example, CPLDs and antifuse devices. Other PLDs, called ASICs (Application Specific Integrated Circuits), are programmed by applying one or more customized metal layers to a previously manufactured standard base. Regardless of the type of PLD used, the configuration data used to program the device is generally provided in one or more computer programs.
Whatever the type of PLD used in a customer design, a significant benefit of programmable devices is the fact that the time required to design and implement a circuit is typically much shorter than the time required to design and manufacture a custom device. Therefore, in recent years PLD manufacturers have provided pre-designed “macros”, i.e., files that include programming information to implement a particular function using some or all of the resources of a targeted PLD. Some macros are configurable, meaning that the user can select certain functions to be included, set parameters such as bit width, or select a target PLD from a list of supported PLDs. The macro program generates a configuration data file that varies depending on the information provided by the user.
Efficient use of PLD resources is important, because such efficiency can allow a user design to fit into a smaller (and less expensive) PLD. For some very large designs, inefficient resource usage can result in an implementation so large it cannot be implemented in any PLD available from a given PLD provider. Therefore, a PLD provider providing macros that more efficiently implement common user functions in its own PLDs has a marketing advantage over its competitors. Hence, efficient PLD implementations of common functions are highly desirable.
One function often used in user designs is the ALU (Arithmetic Logic Unit) function. An ALU circuit typically supports several different functions, one of which is selected using operator input signals. Supported functions can include, for example, an adder function, a subtractor function, an increment function, a decrement function, a multiplexer function, and logical functions such as AND, OR, and XOR.
Patterson and Hennessy show and describe several ALU circuits in pages 182-198 of “Computer Organization & Design: The Hardware/Software Interface”, published in 1994 by Morgan Kaufmann Publishers, Inc., which pages are hereby incorporated by reference.
Typically, ALU functions are provided for a single bit (e.g., two one-bit input signals are added together) in a one-bit ALU circuit. Two or more of these one-bit circuits are then combined to provide a multi-bit ALU function. The width of an ALU circuit can be, for example, 8, 16, or 32 bits. Therefore, an efficient implementation of a one-bit ALU function is highly desirable in terms of efficiently using PLD resources.
SUMMARY OF THE INVENTION
The invention provides structures and methods that implement an ALU (Arithmetic Logic Unit) circuit in a PLD (Programmable Logic Device) while using only one PLD logic cell to implement a one-bit ALU function. The term “logic cell” is used to indicate a group of configurable logic elements including one function generator (e.g., a look-up table) and one memory storage device (e.g., a flip-flop or a latch), with supporting logic. The logic capacity of a PLD is often specified as a number of “logic cells”.
The ALU circuit has two data input signals and two operator input signals that select between the adder, subtractor, and other logical functions. A result bit provides the result of the addition, subtraction, or logical function as selected by the values of the two operator input signals. A carry chain is provided for combining the one-bit ALU circuits to generate multi-bit ALUs. All of this functionality is implemented in a single PLD logic cell per ALU bit.
According to a first embodiment of the invention, an ALU circuit includes a four-input function generator, an AND gate, a carry multiplexer, and an XOR gate.
The four-input function generator has as input signals first and second data input signals and first and second operator input signals. The function generator is configured to implement an XOR function, a first multiplexer function, and a second multiplexer function. The XOR function is an XOR function of the first and second data input signals and the first operator input signal. The first multiplexer function selects between first and second logical functions of the first and second data input signals, providing a result of the first logical function when the first operator input signal is high and providing a result of the second logical function when the first operator input signal is low. The second multiplexer function selects between the XOR output signal and the first multiplexer output signal, providing the XOR output signal when the second operator input signal is high and providing the first multiplexer output signal when the second operator input signal is low. The output of the second multiplexer is coupled to the function generator output terminal.
The AND gate is coupled to the first data input terminal and the second operator input terminal of the logic cell and has an AND output terminal. The carry multiplexer has a “zero” data input terminal coupled to the AND output terminal, a “one” data input terminal coupled to the carry-in terminal of the logic cell, an output terminal coupled to the carry-out terminal of the logic cell, and a select input terminal coupled to the function generator output terminal. The XOR circuit has a first input terminal coupled to the function generator output terminal, a second input terminal coupled to the carry-in terminal, and an output terminal coupled to the result output terminal of the logic cell.
In one embodiment, the first logical function is simply the first data input signal, and the second logical function is the second data input signal. In another embodiment, the logic implemented by the function generator includes logic gates coupled between the first and second data input terminals and the first multiplexer. Thus, the first multiplexer function selects between two different logical functions of the first and second data input signals. In one embodiment, the first multiplexer selects between the AND function and the OR function of the first and second data input signals.
One PLD that can be used to implement the described circuit in a single logic cell is the Virtex™-II Field Programmable Gate Array (FPGA) provided by Xilinx, Inc. The Virtex-II CLB includes four similar slices, each including two logic cells. Each logic cell includes one four-input function generator implemented as a look-up table, as well as additional logic including at least one AND gate, multiple

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