Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-07-30
2004-01-20
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S712000, C438S720000
Reexamination Certificate
active
06680257
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to processing methods for fabricating non-volatile semiconductor memory devices having a floating gate, such as EPROMs and Flash EEPROMS. More particularly, it relates to an improved method for eliminating problems associated with self-aligned source (SAS) photoresist process used in the fabrication of Flash EEPROMS.
2. Description of the Prior Art
As is generally well-known in the art, non-volatile memory devices using a floating gate for the storage of charges thereon such as EPROMs (erasable programmable read-only memories), EEPROMS (electrically, erasable programmable read-only memories) or Flash EEPROMS have emerged in recent years. In such a conventional Flash EEPROM memory device, a plurality of such one-transistor memory cell may be formed on a P-type semiconductor substrate in which each cell is comprised of an n+ drain region and an n+ source region both formed integrally within the substrate. A relatively thin gate dielectric layer is interposed between a top surface of the substrate and a conductive polysilicon floating gate. A polysilicon control gate is insulatively supported above the floating gate by a second dielectric layer. A channel region in the substrate separates the drain and source regions.
As is well known, Flash EEPROM devices have become very useful in forming many electrical and electronic products. In view of this trend, there has arisen a high demand on memory device manufacturers to develop Flash EEPROM devices with higher and higher densities so as to enhance their performance as well as to reduce their manufacturing cost. One of the typical ways of increasing the density of the memory devices has been accomplished through the use of a so-called self-aligned source (SAS) etching process.
An example of this SAS etching process is described and illustrated in U.S. Pat. No. 5,534,455 to David K. Y. Liu entitled “METHOD FOR PROTECTING A STACKED GATE EDGE IN A SEMICONDUCTOR DEVICE FROM SELF ALIGNED SOURCE (SAS) ETCH,” which is hereby incorporated by reference in its entirety. This '455 patent discloses a process and system for protecting a stacked gate edge of a semiconductor device. The stacked gate edge is provided on the semiconductor device. A source implant is performed to ensure uniform profile prior to a self-aligned source (SAS) etch. Next, a polysilicon spacer is formed on the stacked gate edge prior to the SAS etch. Then, a SAS etch is performed on the semiconductor device. As a result, the tunnel oxide integrity has been improved and the source junction oxide integrity has been made more uniform since the silicon around the source region has not been gouged away or damaged.
However, the process sequence used in the '455 patent of the prior art is not concerned with solving the problems caused by the SAS photoresist process associated with the SAS etch. The process sequence used in this prior art can cause contamination of the tunnel oxide due to the SAS photoresist material contacting the edges of the stacked gates. Further, the removal and cleaning of the photoresist after it has been developed and resist strip from unwanted areas will be difficult to achieve and can leave resist residues. The resist residues will cause blocking of a subsequent implantation in the field oxide regions where it should have been removed.
Accordingly, there has arisen a need for providing an improved method for fabricating semiconductor memory devices which eliminates all of the negative impacts relative to the SAS photoresist process used in the Flash EEPROM process. It would also be expedient that the improved method be capable of being performed without the addition of any new process steps and require only minimal modifications to the existing process steps.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide an improved method for eliminating problems associated with the SAS photoresist process used in the fabrication of Flash EEPROM memory devices which overcomes the disadvantages of the prior art.
It is an object of the present invention to provide an improved method for fabricating semiconductor memory devices which eliminates all of the negative impacts relative to the SAS photoresist process used in the Flash EEPROM process.
It is another object of the present invention to provide an improved method for fabricating semiconductor memory devices which can be performed with only minimal modifications to existing process steps.
It is still another object of the present invention to provide an improved method for fabricating a semiconductor memory device which eliminates contamination of the tunnel oxide by the SAS photoresist process and prevents blocking of implantation due to the resist residue from the SAS process.
In a preferred embodiment of the present invention, there is provided a method of eliminating contamination of tunnel oxide in stacked gates due to SAS photoresist process and preventing of n+ implantation caused by resist residue from the SAS photoresist process in fabricating of a semiconductor memory device. Stacked gates are provided on the semiconductor memory device which are separated by trenches. Source and drain implants are performed on the semiconductor memory device. The trenches between the stacked gates are filled with oxide so as to cover the entire surface of the semiconductor memory device. The entire surface of the semiconductor memory device is planarized so as to provide a flat top surface. A SAS photoresist mask is applied to the flat top surface of the semiconductor memory device. A SAS etch is performed on the semiconductor memory device so as to remove the oxide. A source connection implant is performed so as to provide a common source line.
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patent: 5482881 (1996-01-01), Chen et al.
patent: 5534455 (1996-07-01), Liu
patent: 5674767 (1997-10-01), Lee et al.
patent: 5700704 (1997-12-01), Ikeda et al.
patent: 5736442 (1998-04-01), Mori
patent: 6013551 (2000-01-01), Chen et al.
patent: 6030869 (2000-02-01), Odake et al.
patent: 6365457 (2002-04-01), Choi
patent: 09069578 (1997-03-01), None
Chin Davis
EON Silicon Devices, Inc.
Norton Nadine G.
Vinh Lan
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