Alternative methodology for defect simulation and system

Details Alternative methodology for defect simulation and system Alternative methodology for defect simulation and system

2008-04-08

2008-04-08

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C382S149000

Reexamination Certificate

active

11099834

ABSTRACT:
A system for defect simulation is provided. A defect layout generator generates a defect layout comprising a given number of spot defects of a given size. A processor first compares the defect layout and a provided circuit layout comprising a plurality of conductive regions. The processor further determines whether the spot defects are located on the conductive regions, and determines whether short-circuits and/or open circuits are caused by the spot defects in the conductive regions.

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