Alternating reference wordline scheme for fast DRAM

Details Alternating reference wordline scheme for fast DRAM Alternating reference wordline scheme for fast DRAM

2001-05-14

2002-12-31

Tran, Michael (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S190000

Reexamination Certificate

active

06501675

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to dynamic random access memories (DRAMs) and, more particularly to a fast DRAM which uses an alternating reference cells and a ground-sensing technique.
2. Description of the Related Art
Dynamic random access memory (DRAM) performance is a well known limitation to computer system performance. Processor speeds are rapidly outpacing main memory performance, with both processor designers and system manufacturers developing higher performance memory subsystems in an effort to minimize performance limitations due to the slower DRAM devices. Ideally, the memory performance would match or exceed processor performance, i.e., a memory cycle time would be less than one processor clock cycle. This is almost never the case and, so, the memory is a system bottleneck. While microprocessor speed has continued to increase almost exponentially, DRAM performance lacks a corresponding improvement. However, since DRAM memories continue to offer the highest density and lowest cost per bit they remain the most popular choice for computer system main memories.
By way of background, in their simplest form, a single DRAM memory cell comprises a single transistor and a single capacitor. Depending on the convention used, if a charge is stored on the capacitor the cell is said to store a 1-bit. If no charge is present, the cell is said to store a 0-bit. Since the charge on the capacitor dissipates over time, DRAM systems require additional overhead circuitry to periodically refresh the charge on the capacitor. With modern lower voltage devices it is difficult to distinguish the difference between 0 and a 1. Therefore, two bit lines are typically used for each bit with the first in the bit line pair known as bit line true (BLT) and the other being the bit line complement (BLC). In this manner, it is actually the difference between these two bit lines that determines the stored bit value.
The DRAM memory system is actually realized by incorporating many of such DRAM cell pairs in an array. Any pair in the array is addressable by row and column. The rows of the array are referred to a “word-lines” and the columns of the array are referred to as “bit-lines”. The bit lines occur in pairs, namely, bit-line true (BLT) and a bit-line complement (BLC). When a particular word-line is selected, all of the bit line pairs in that row are selected by a row address strobe (RAS) signal. Thereafter, a particular bit-line pair is selected by the column address strobe (CAS) which identifies the desired true and complement cell pair in the selected word-line to be read from or written to. A sense amplifier is connected the true and complement bit-lines. The charge transferred from each memory cell to each bit-line in the pair is differentially amplified and latched by the sense amplifier thus reading out the bit.
Over the years, many improvements have been made to DRAM array architectures, address latching and decoding circuits, sensing schemes, data paths, and the like which have greatly increased the speed, reliability and performance of DRAM memories. In particular, engineers have minimized operational power and reduced noise by using what is commonly referred to as half-Vdd (i.e. Vdd/2) sensing schemes. In a Vdd/2 sensing scheme, the bit lines are precharged to a voltage of Vdd/2 prior to reading. With Vdd/2 sensing when a particular cell is selected the charge stored on the memory cell capacitor will be shared with the bit line thus causing the voltage on the bit line to rise above or fall below Vdd/2. This difference is then sensed and amplified to read the bit. While providing benefits such as noise reduction, signal development is slowed due to the time required to precharge the bit lines and lower gain of the cell pass devices.
As is apparent from the above discussion, this type of DRAM system experiences what is commonly referred to as a destructive read. That is, when a particular cell is selected, the charge on the cell capacitor is shared or discharged onto the bit line to be read. Hence, if a charge was stored on the capacitor indicating storage of a “1”, after the read the charge is no longer present. Thus, after a read occurs, additional circuitry is required to rewrite the bit back into the memory cell. Traditionally, this rewrite step was done in the same cycle as the read.
So called “fast” DRAM memories have been developed that do not require signal development and write-back of the cell within the same DRAM cycle. The write-back of the cell occurs during a different cycle. As a result, by separating the read and write-back of the cell into two unique cycles the cycle time is decreased by roughly half of a conventional DRAM.
As shown in
FIG. 1
, there is shown a single column of a fast DRAM memory array. Each memory location comprises a bit-line true (BLT)
10
and a bit-line complement (BLC)
12
line, respectively, connected to a sense amplifier shown in box
14
. In addition to a sense amplifier, the box
14
may also include additional circuitry such as isolation devices and bit line precharge circuitry. A plurality of wordlines, labeled WORDLINE-
0
to WORDLINE-n, share access to the BLT
10
and BLC
12
. Each DRAM cell comprises a single capacitor
16
0-n
and a single FET transistor
18
0-n
used to connect the capacitor to either the BLT
10
or the BLC
12
when the appropriate wordline is selected. Also shown in each DRAM cell is a resistor
20
0-n
. However, this is a parasitic resistor inherent to the device and not an actual resistor purposely positioned.
This “fast” DRAM may only be implemented with a half-VDD (Vdd/2) sensing scheme where the bit-lines are precharged to Vdd/2. As noted above, this technique has several disadvantages including slow signal development time, limited low voltage functionality, slow sensing performance from small overdrive, and small signal margins which results in a more sensitive design at lower voltages.
An alternative, perhaps more desirable approach would be to use a ground-sensing scheme. In ground-sensing, each of the bit line pairs are precharged or “restored” to ground potential prior to a read. Thereafter a reference cell is, activated in tandem with the word line to place a reference voltage on one of the bit-lines, either the BLT or BLC.
However, ground sensing will not work with this circuit. As an example, if one were to try and read a 1-bit out from the BLT
10
on WORDLINE-
0
, using ground-sensing, both BLT
10
and BLC
12
would be restored to ground (i.e. brought to ground potential). WORDLINE-
0
is brought active and the charge stored on capacitor
16
0
would be discharged to the BLT through transistor
18
0
. Assuming ideal conditions and thus neglecting the effects of parasitic resistance
20
0
, the voltage on BLT would be:
V
BLT
=
V
C
⁢
(
C
cell
C
cell
+
C
BLT
)
where V
c
is the voltage on the cell capacitor
16
0
,
C
cell
is the capacitance of capacitor
16
0
, and
C
BLT
is the capacitance of the BLT itself.
The sense amplifier
14
will be set and compares the voltages on BLT
10
and BLC
12
. Based on the difference in voltages on BLT
10
and BLC
12
, the sense amplifier circuitry
14
will output a signal amplifying BLT
10
to a full rail 1-bit signal and BLC
12
to a full rail 0-bit signal thus signifying that a 1-bit was stored in
16
0
. However, as is apparent, ground sensing does not work well in the event a 0-bit is stored in
16
0
since in this case both BLT
10
and BLC
12
will have 0-volts on them after reading a 0-bit. Thus, the sense amplifier has nothing to compare leading to unpredictable results since there is no way to determine which of BLT
10
or BLC
12
should be amplified to rail potential.
SUMMARY OF THE INVENTION
The present invention is directed to a fast DRAM memory which uses ground-sensing as opposed to traditional Vdd/2 sensing. A selected DRAM cell connects to a bit-line true (BLT) or a bit-line complement (BLC). A ground-sensing technique is used wherein at the start of each cycle the BLT and

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