Alternate 4-terminal JFET geometry to reduce gate to source...

Details Alternate 4-terminal JFET geometry to reduce gate to source... Alternate 4-terminal JFET geometry to reduce gate to source...

2009-10-07

2011-11-15

Soward, Ida M (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

C257S257000, C257S263000, C257S277000, C257S504000, C257SE27148, C257SE29265, C257SE29314

Reexamination Certificate

active

08058674

ABSTRACT:
A 4-Terminal JFET includes a substrate having a first conduction type and an upper layer having a second, opposite, conduction type over the substrate. A gate and a source are embedded in the upper layer. A gate pad is electrically connected to the gate. A region, which has a first conduction type, is formed in the upper layer and separates the upper layer into two sections. This region reduces the overall capacitance between the gate pad and the source. Reduced overall gate to source capacitance can result in reduced noise amplification in the JFET.

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