Alloy barrier layers for semiconductors

Details Alloy barrier layers for semiconductors Alloy barrier layers for semiconductors

1998-10-08

2002-03-26

Whitehead, Jr., Carl (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S767000, C257S771000, C257S753000, C257S740000, C257S761000, C257S768000, C257S915000, C438S597000, C438S627000, C438S653000, C438S629000, C438S643000, C438S648000, C438S656000, C438S675000

Reexamination Certificate

active

06362526

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductors and more specifically to barrier metals for preventing diffusion of conductive materials.
BACKGROUND ART
While manufacturing integrated circuits, after the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called “metallization”, and is performed using a number of different photolithographic and deposition techniques.
In one connection process, which is called a “dual damascene” technique, two channels of conductive materials, are positioned in vertically separated planes perpendicular to each other and interconnected by a vertical “via” at their closest point.
The first channel part of the dual damascene process starts with the placement of a first channel dielectric layer, which is typically an oxide layer, over the semiconductor devices. A first damascene step photoresist is then placed over the oxide layer and is photolithographically processed to form the pattern of the first channels. An anisotropic oxide etch is then used to etch out the channel oxide layer to form the first channel openings. The damascene step photoresist is stripped and an optional thin adhesion layer is deposited to coat the walls of the first channel opening to ensure good adhesion and electrical contact of subsequent layers to the underlying semiconductor devices. A barrier layer is then deposited on the adhesion layer improve the formation of subsequently deposited conductive material and to act as a barrier material to prevent diffusion of such conductive material into the oxide layer and the semiconductor devices. A first conductive material is then deposited and subjected to a chemical-mechanical polishing process which removes the first conductive material above the first channel oxide layer and damascenes the first conductive material in the first channel openings to form the first channels.
The via formation step of the dual damascene process starts with the deposition of a thin stop nitride over the first channels and the first channel oxide layer. Subsequently, a separating oxide layer is deposited on the stop nitride. This is followed by deposition of a thin via nitride. Then a via step photoresist is used in a photolithographic process to designate round via areas over the first channels.
A nitride etch is then used to etch out the round via areas in the via nitride. The via step photoresist is then removed, or stripped. A second channel dielectric layer, which is typically an oxide layer, is then deposited over the via nitride and the exposed oxide in the via area of the via nitride. A second damascene step photoresist is placed over the second channel oxide layer and is photolithographically processed to form the pattern of the second channels. An anisotropic oxide etch is then used to etch the second channel oxide layer to form the second channel openings and, during the same etching process to etch the via areas down to the thin stop nitride layer above the first channels to form the via openings. The damascene photoresist is then removed, and a nitride etch process removes the nitride above the first channels in the via areas. An adhesion layer is then deposited to coat the via openings and the second channel openings. Next, a barrier layer is deposited on the adhesion layer. This is followed by a deposition of the second conductive material in the second channel openings and the via openings to form the second channel and the via. A second chemical-mechanical polishing process leaves the two vertically separated, horizontally perpendicular channels connected by cylindrical vias.
The use of the dual damascene technique eliminates metal etch and dielectric gap fill steps typically used in the metallization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metallization materials, such as copper, which are very difficult to etch.
One drawback of using copper is that copper diffuses rapidly through various materials. Unlike aluminum, copper also diffuses through dielectrics, such as oxide. When copper diffuses through dielectrics, it can cause damage to neighboring devices on the semiconductor substrate. To prevent diffusion, materials such as tantalum nitride (TaN), titanium nitride (TiN), or tungsten nitride (WN) are used as barrier materials for copper. A thin adhesion layer formed of an adhesion material, such as tantalum (Ta), titanium (Ti), or tungsten (W) is first deposited on the dielectrics or vias to ensure good adhesion and good electrical contact of the subsequently deposited barrier layers to underlying doped regions and/or conductive channels. Adhesion/barrier layer stacks formed of adhesion/barrier materials such Ta/TaN, Ti/TiN, and W/WN have been found to be useful as adhesion/barrier material combination for copper interconnects.
However, even with the various types of barrier layers, copper is still subject to strong electro-migration due to poor surface adhesion to the barrier layers. A solution, which would form a copper conductive channel with better surface adhesion and thus longer electromigration lifetime, has been long sought The difficulty is that many approaches result in an increase in the electrical resistance. As the semiconductor industry is moving from aluminum to copper and other type of materials with greater electrical conductivity and diffusiveness through dielectrics, it is becoming more pressing that a solution be found.
DISCLOSURE OF THE INVENTION
The present invention provides alloy barrier layer for semiconductors and a manufacturing method therefor. The alloy is first disposed on the semiconductor, processed to be infused by a barrier improving material, followed by the alloy being further disposed to complete the barrier before the disposition of the conductive layer.
The present invention provides tantalum-titanium alloy barrier layer for copper conductors in semiconductors and a manufacturing method therefor. The tantalum-titanium alloy is first deposited on the semiconductor dielectric, nitrided, the deposition of the tantalum-titanium alloy is completed and the copper metalization is deposited on the tantalum titanium alloy. The titanium forms a superb bond with the dielectric, the tantalum-titanium nitride forms a superb diffusion barrier, and the titanium forms a superb bond with the copper conductor.
The present invention provides an alloy which provides superb adhesion of the barrier layer with the semiconductor dielectric.
The present invention further provides an alloy having a superb copper diffusion barrier as part of the barrier layer.
The present invention further provides superb adhesion between the alloy and the conductive material while suppressing surface diffusion of the conductive material.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.


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patent: 6258710 (2001-07-01), Rathore et al.
Brouillard “Thin Metallurgy with Sandwich Barrier Layers” IBM Technical disclosure Bulltin 21, 576 (Jul. 1978).

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